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    CY7C1265V18 Search Results

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    CY7C1265V18 Price and Stock

    Infineon Technologies AG CY7C1265V18-450BZC

    IC SRAM 36MBIT PAR 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1265V18-450BZC Tray 105
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    • 1000 $54.60962
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    Infineon Technologies AG CY7C1265V18-400BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1265V18-400BZC Tray 105
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    Rochester Electronics LLC CY7C1265V18-400BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1265V18-400BZC Tray 6
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    Infineon Technologies AG CY7C1265V18-400BZXC

    IC SRAM 36MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1265V18-400BZXC Tray 105
    • 1 -
    • 10 -
    • 100 -
    • 1000 $54.60962
    • 10000 $54.60962
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    Cypress Semiconductor CY7C1265V18-400BZC

    CY7C1265V18-400BZC
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    Verical CY7C1265V18-400BZC 138 7
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    • 1000 $52.75
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    CY7C1265V18-400BZC 21 7
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    Rochester Electronics CY7C1265V18-400BZC 159 1
    • 1 $49.65
    • 10 $49.65
    • 100 $46.67
    • 1000 $42.2
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    CY7C1265V18 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1265V18 Cypress Semiconductor 36-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Original PDF
    CY7C1265V18-400BZC Cypress Semiconductor 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Original PDF
    CY7C1265V18-400BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 400MHZ 165FBGA Original PDF

    CY7C1265V18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1276V18 CY7C1263V18 CY7C1265V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth


    Original     		PDF CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit CY7C1276V18/CY7C1263V18/CY7C1265V18 CY7C1256AV18

    CY7C1263V18

    Abstract: CY7C1261V18 CY7C1265V18 CY7C1276V18
    Text: CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features • Configurations With Read Cycle Latency of 2.5 cycles: Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit CY7C1261V18 CY7C1263V18 CY7C1263V18 CY7C1261V18 CY7C1265V18 CY7C1276V18

    CY7C1263V18-400

    Abstract: No abstract text available
    Text: CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,


    Original     		PDF CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit CY7C1263V18-400

    CY7C1261V18

    Abstract: CY7C1263V18 CY7C1265V18 CY7C1276V18
    Text: CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,


    Original     		PDF CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit CY7C1261V18, CY7C1276V18, CY7C1263V18, CY7C1265V18 CY7C1261V18 CY7C1263V18 CY7C1276V18

    CY7C1261V18

    Abstract: CY7C1263V18 CY7C1265V18 CY7C1276V18
    Text: CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features • Configurations With Read Cycle Latency of 2.0 cycles: Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit CY7C1261V18 CY7C1263V18 CY7C1261V18 CY7C1263V18 CY7C1265V18 CY7C1276V18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1263V18 CY7C1265V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth


    Original     		PDF CY7C1263V18 CY7C1265V18 36-Mbit