CY7C1161V18 Search Results
CY7C1161V18 Datasheets (1)
Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | |
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CY7C1161V18 |
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18-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) | Original |
CY7C1161V18 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-06582 Spec Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT QDR TM -II+ SRAM 4-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Jayasree Nayar (njy) Replaced by: NONE CY7C1161V18, CY7C1176V18 |
Original |
CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 | |
Contextual Info: CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth |
Original |
CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1161V18, CY7C1176V18, CY7C1163V18, CY7C1165V18 | |
CY7C1161V18
Abstract: CY7C1163V18 CY7C1165V18 CY7C1176V18
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Original |
CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1161V18 CY7C1163V18 CY7C1165V18 CY7C1176V18 | |
CY7C1161V18
Abstract: CY7C1163V18 CY7C1165V18 CY7C1176V18
|
Original |
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 18-Mbit CY7C1161V18 CY7C1163V18 CY7C1165V18 CY7C1176V18 |