CY7C1012DV33 Search Results
CY7C1012DV33 Price and Stock
Infineon Technologies AG CY7C1012DV33-10BGXITIC SRAM 12MBIT PARALLEL 119PBGA |
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CY7C1012DV33-10BGXIT | Reel |
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CY7C1012DV33 Datasheets (4)
Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | |
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CY7C1012DV33 |
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12-Mbit (512K x 24) Static RAM | Original | |||
CY7C1012DV33-10BGXI |
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Memory, Integrated Circuits (ICs), IC SRAM 12MBIT 10NS 119BGA | Original | |||
CY7C1012DV33-10BGXIT |
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Memory, Integrated Circuits (ICs), IC SRAM 12MBIT 10NS 119BGA | Original | |||
CY7C1012DV33-8BGXC |
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12-Mbit (512K x 24) Static RAM | Original |
CY7C1012DV33 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: CY7C1012DV33 12-Mbit 512 K x 24 Static RAM 12-Mbit (512 K × 24) Static RAM Functional Description Features The CY7C1012DV33 is a high performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE1, CE2, and CE3). |
Original |
CY7C1012DV33 12-Mbit CY7C1012DV33 I/O15, I/O16â I/O23. | |
CY7C1012DV33Contextual Info: CY7C1012DV33 12-Mbit 512K X 24 Static RAM Functional Description Features • High speed ❐ tAA = 8 ns ■ Low active power ❐ ICC = 225 mA at 8 ns ■ Low CMOS standby power ❐ ISB2 = 25 mA ■ Operating voltages of 3.3 ± 0.3V ■ 2.0V data retention |
Original |
CY7C1012DV33 12-Mbit 119-Ball CY7C1012DV33 | |
CY7C1012DV33-10BGXI
Abstract: SRAM TTL
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Original |
CY7C1012DV33 12-Mbit CY7C1012DV33 I/O15, I/O16 I/O23. CY7C1012DV33-10BGXI SRAM TTL | |
Contextual Info: CY7C1012DV33 PRELIMINARY 12-Mbit 512K X 24 Static RAM Features power-down feature that significantly consumption when deselected. • High speed reduces power Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write |
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CY7C1012DV33 12-Mbit 119-ball | |
CY7C1012DV33Contextual Info: CY7C1012DV33 PRELIMINARY 12-Mbit 512K X 24 Static RAM Features power-down feature that significantly consumption when deselected. • High speed reduces power Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write |
Original |
CY7C1012DV33 12-Mbit 119-ball CY7C1012DV33 | |
CY7C1012DV33Contextual Info: CY7C1012DV33 12-Mbit 512K X 24 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 25 mA The CY7C1012DV33 is a high performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately |
Original |
CY7C1012DV33 12-Mbit CY7C1012DV33 I/O15, I/O16 I/O23. | |
CY7C1012DV33Contextual Info: CY7C1012DV33 PRELIMINARY 12-Mbit 512K X 24 Static RAM Features power-down feature that significantly consumption when deselected. • High speed reduces power Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write |
Original |
CY7C1012DV33 12-Mbit CY7C1012DV33 | |
Contextual Info: CY7C1012DV33 12-Mbit 512 K x 24 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1012DV33 is a high performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE1, CE2, and CE3). |
Original |
CY7C1012DV33 12-Mbit CY7C1012DV33 I/O15, I/O16 I/O23. | |
Contextual Info: CY7C1012DV33 12-Mbit 512K X 24 Static RAM Functional Description Features • High speed ❐ tAA = 8 ns ■ Low active power ❐ ICC = 225 mA at 8 ns ■ Low CMOS standby power ❐ ISB2 = 25 mA ■ Operating voltages of 3.3 ± 0.3V ■ 2.0V data retention |
Original |
CY7C1012DV33 12-Mbit CY7C1012DV33 |