CY28343OCT Search Results

CY28343OCT Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY28343OCT		Cypress Semiconductor	Zero Delay SDR/DDR Clock Buffer		Original	PDF

CY28343OCT Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY28343 Zero Delay SDR/DDR Clock Buffer Features • External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for DDR. • SMBus interface enables/disables outputs. • Conforms to JEDEC SDR/DDR specifications • Low jitter, low skew	Original	CY28343 CY28343	PDF
CY28343 Abstract: CY28343OC CY28343OCT Contextual Info: CY28343 Zero Delay SDR/DDR Clock Buffer Features • External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for DDR. • SMBus interface enables/disables outputs. • Conforms to JEDEC SDR/DDR specifications • Low jitter, low skew	Original	CY28343 CY28343 CY28343OC CY28343OCT	PDF

Catalog Datasheet

Type

Document Tags

PDF

Contextual Info: CY28343 Zero Delay SDR/DDR Clock Buffer Features • External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for DDR. • SMBus interface enables/disables outputs. • Conforms to JEDEC SDR/DDR specifications • Low jitter, low skew

Original

CY28343 CY28343

PDF

CY28343

Abstract: CY28343OC CY28343OCT
Contextual Info: CY28343 Zero Delay SDR/DDR Clock Buffer Features • External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for DDR. • SMBus interface enables/disables outputs. • Conforms to JEDEC SDR/DDR specifications • Low jitter, low skew

Original

CY28343 CY28343 CY28343OC CY28343OCT

PDF