COPROCESSOR Search Results

ARM926EJS

Abstract: ARM926EJ-S cdm-9 NAND FLASH Controller i2s1tx_clk
Contextual Info: LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 01 — 6 February 2009 Preliminary data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high

km3702

Abstract: KM3701 KM3702A Quadrature Encoder Zero clamp KM3702AD KM3702AD/AQ
Contextual Info: r&TOKO KM3702AD/AQ INTERPOLATION COPROCESSOR FEATURES APPLICATIONS • Interfaces Directly with an 8 Bit Microprocessor ■ Motion Control Systems ■ Wide Application Range ■ Robotics ■ Reduced Number of Counter ICs ■ Drawing Machines ■ Reduced Parts Count

VFP9-S

Abstract: CP15 ARM Architecture Reference Manual VFP9S 0x00000000b
Contextual Info: VFP9-S Vector Floating-point Coprocessor r0p2 Technical Reference Manual Copyright 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0238B VFP9-S r0p2 Vector Floating-point Coprocessor Technical Reference Manual Copyright © 2002, 2003 ARM Limited. All rights reserved.

8087 data types

Abstract: 8087 coprocessor instruction set 8087 coprocessor architecture bcd addition program of 8086 intel 8087 architecture coprocessor intel 8087 amd 8086 8087 architecture and configuration 8284A clock generator driver 8086 interfacing of memory devices with 8086
Contextual Info: 8087 Numeric Data Coprocessor ÌAPX86 Family DISTINCTIVE CHARACTERISTICS • • • High perform ance arithm etic and transcendental fu n c­ tions in hardware Supports 8-, 16-, 32-, 64-bit integer Performs 32-, 64-, 80-bit floating point calculations conforming to !EEE standard

8087 architecture and configuration

Abstract: 8087 coprocessor architecture black diagram of ic 8086 1QS01 8087 data types
Contextual Info: 8087 Numeric Data Coprocessor ¡APX86 Family DISTINCTIVE CHARACTERISTICS • • • High performance arithmetic and transcendental func­ tions in hardware Supports 8-, 16-, 32-, 64-bit integer Performs 32-, 64-, 80-bit floating point calculations conforming to IEEE standard

intel 80287

Abstract: ibm at motherboard 80286 intel 80286 TECHNICAL intel 80287 arithmetic coprocessor 80C287-16 ic 80286 intel 80C287 coprocessor
Contextual Info: 80C287 Coprocessor/Software Accelerator Performance Benchmarks by Linda Bishop INTRODUCTION The math coprocessor/software accelerator performing floating-point arithmetic helps your 80286-based com­ puter do more work in less time. A computer with a high-speed math coprocessor installed can perform

80286based

Abstract: JC EG
Contextual Info: a AMD 80C287 Advanced Micro Devices 80-Bit CMOS Math Coprocessor DISTINCTIVE CHARACTERISTICS • High-performance CMOS process yields 10-MHz and 12-MHz speed grades ■ Available In space-saving 44-pin PLCC as well as 40-pin DIP ■ BO-blt numeric accelerator for 80C28&- and

MMCX decoupling TOOL

Abstract: 6691 USB connector
Contextual Info: AM3517/05 ARM Microprocessor www.ti.com SPRS550 – OCTOBER 2009 1 AM3517/05 ARM Microprocessor 1.1 Features AM3517/05 ARM Microprocessor: – Software Compatible with OMAPTM 3 Processors* – MPU Subsystem • 500-MHz ARM Cortex-A8 Core • NEON SIMD Coprocessor and Vector

79R3000

Contextual Info: RISC CPU PROCESSOR IDT79R3000A IDT79R3000AE Integrated Device Technology, Inc. FEATURES: Dynamically able to switch between Big- and Little- Endian byte ordering conventions. Coprocessor Interface— The IDT79R3000A generates all addresses and handles memory interface control for up to

Contextual Info: ¡n tg l. 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

coprocessor

Contextual Info: in y Intel387 SX MATH COPROCESSOR N e w A u to m a tic P o w e r M a n a g e m e n t — L o w P o w e r C o n su m p tio n — T y p ic a lly 100 m A in D y n a m ic M o de, an d 4 m A in Id le M o d e S o c k e t C o m p a tib le w ith In te l3 8 7 Fam ily

SAB-R3010

Contextual Info: il* e 23 SIEMENS High-Performance Floating-Point Coprocessor SAB-R3010A based on Advanced RISC Architecture with four Independent Arithmetic Functional Units Advance Inform ation Fully conform s to ANSI/IEEE standard 754-1985 tor binary floating-point arithmetic

Contextual Info: intJ 80C187 80-BIT MATH COPROCESSOR • High Performance 80-Bit Internal Architecture ■ Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic ■ Upward Object-Code Compatible from 8087 ■ Fully Compatible with 387DX and 387SX Math Coprocessors. Implements all 387

m8087-2

Contextual Info: M8087 NUMERIC DATA PROCESSOR Military • High Performance Numeric Data Coprocessor ■ Standard M8086 Instruction Set Plus Arithmetic, Trigonometric, Exponential, and Logarithmic Instructions for All Data Types ■ All 24 Addressing Modes Available with M8086, M8088, M80186 CPUs

atmel 432

Contextual Info: AT40K05AL, AT40K10AL AT40K20AL, AT40K40AL 5K – 50K Gates Coprocessor FPGA with FreeRAM SUMMARY DATASHEET Features  Ultra High Performance ̶ ̶ System Speeds to 100MHz Array Multipliers > 50MHz 10ns Flexible SRAM Internal Tri-state Capability in Each Cell

DSP56300

Abstract: DSP56307 DSP56311 MSC8101 SC140
Contextual Info: Order Number: AN2084/D Rev. 0, 3/2001 MOTOROLA Semiconductor Products Sector Application Note Differences Between the DSP56300 and MSC8101 Enhanced Filter Coprocessors EFCOPs By Tina M. Redheendran The Enhanced Filter Coprocessor (EFCOP) is a general-purpose,

HS488

Abstract: NAT4882 TNT4882C
Contextual Info: Combination GPIB Controller/Analyzer for ISA AT-GPIB/TNT+ Features AT-GPIB/TNT+ Processor PC AT ISA , Plug and Play ISA Intel 386 or higher, math coprocessor required Overview The AT-GPIB/TNT+ combines the functionality of the AT-GPIB/TNT (Plug and Play) IEEE 488.2 Controller

INS16Cx50

Abstract: cea f23 rtc 1301 cea g22 matrix m21 ARM926EJ-S LPC3180 LPC3180FEL320 PL080 difference between arm7 and arm9
Contextual Info: LPC3180 16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface Rev. 01 — 2 June 2006 Preliminary data sheet 1. General description The LPC3180 is an ARM9-based microcontroller for embedded applications requiring

MAZ80510ML

Abstract: irf7832 AN6041 POWR1014A ZXCT1009 AN6046 zener AMC zener 1v2
Contextual Info: AMC Module Power Management April 2010 Reference Design RD1070 Introduction This reference design describes the use of a Lattice Power Manager II device as a Payload Power Management Coprocessor in an Advanced Mezzanine Card AMC system. The Advanced Mezzanine Card is intended to be

Contextual Info: ü ja lile o . GT-96010 Remote Access Coprocessor Preliminary Revision 1.0 8/12/97 Please contact Galileo Technology for possi b e updates before finalizing a design. FEATURES * Integrated serial communications controller and system core logic device - Direct interface to i960 Jx family of CPUs

ds28el22

Contextual Info: ABRIDGED DATA SHEET DS24L65 DeepCover Secure Authenticator with SHA-256 Coprocessor and 1-Wire Master Function General Description Features DeepCover embedded security solutions cloak sensitive data under multiple layers of advanced physical security to

H1000E

Abstract: TNETA1575 TNETA1585 h1001A-1D
Contextual Info: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 D D D D D D D D D Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections Used With the TNETA1575 to Provide a

Contextual Info: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES • Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections • Used With the TNETA1575 to Provide a Complete Solution for Segmentation and Reassembly of Data on ABR Connections

ORELA 4500

Abstract: toccata WOLA adaptive reference wola WDRC WOLA reference 4500 Series
Contextual Info: AND8384/D Using Block Floating-Point in the WOLA Filterbank Coprocessor http://onsemi.com APPLICATION NOTE WOLA_Start macro, specifying the desired function as a parameter 0 for analysis, 1 for gain application and 2 for synthesis . Consequently, only a “start” macro execution is