CLOCK BUFFER FITS Search Results

CLOCK BUFFER FITS Result Highlights (5)

Part	Manufacturer	Description
74VHCT541AFT	Toshiba Electronic Devices & Storage Corporation	CMOS Logic IC, Octal Buffer, TSSOP20B
74VHC541FT	Toshiba Electronic Devices & Storage Corporation	CMOS Logic IC, Octal Buffer, TSSOP20B
7UL1G125NX	Toshiba Electronic Devices & Storage Corporation	One-Gate Logic(L-MOS), Buffer, XSON6, -40 to 125 degC
7UL1G126NX	Toshiba Electronic Devices & Storage Corporation	One-Gate Logic(L-MOS), Buffer, XSON6, -40 to 125 degC
TC7SET125F	Toshiba Electronic Devices & Storage Corporation	One-Gate Logic(L-MOS), Buffer, SOT-25 (SMV), -40 to 125 degC

CLOCK BUFFER FITS Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY7B185 Abstract: CY7B922 clock buffer FITS CY7B991 CY7B992 EME-6300H SM23B CY7B991-LMB Text: Qualification Report February, 1994 QTP# 92202&93462 Version 2.0 PROGRAMMABLE SKEWCLOCK BUFFER CY7B991 TTL CY7B992 (CMOS) QUALIFICATION REPORT February, 1994 Version 2.0 QTP # 92202/93462 PROGRAMMABLE SKEW CLOCK BUFFER CY7B991 (TTL) CY7B992 (CMOS) CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:	Original	CY7B991 CY7B992 CY7B991 JEDEC22, 30PSIA CY7B185 CY7B922 clock buffer FITS CY7B992 EME-6300H SM23B CY7B991-LMB	PDF
A1280A VKS Abstract: A1280A-CQ172C VKS FPGA CQFP 106 actel a1280a unused pin VKS FPGA CQFP 172 antifuse programming technology A14100A-CQ256C fpga radiation A1280A ACTEL A1280A Text: PRELIMINARY SPACE ELECTRONICS INC. SPACE PRODUCTS RADIATION TOLERANT RAD-PAK FIELD PROGRAMMABLE GATE ARRAYS FEATURES GENERAL DESCRIPTION Radiation Characteristics Actel builds the most reliable field programmable gate arrays FPGAs in the industry, with overall antifuse reliability ratings of less than 10 failures-in-time (FITs), corresponding to a useful life of more than 40 years.	Original	99Rev0 A1280A VKS A1280A-CQ172C VKS FPGA CQFP 106 actel a1280a unused pin VKS FPGA CQFP 172 antifuse programming technology A14100A-CQ256C fpga radiation A1280A ACTEL A1280A	PDF
LCA200K Abstract: 130 nm CMOS standard cell library 10-JK LEA100K CLDCC LEA200K Text: 5304Û04 ÜD m STl 3bb • LLC LSI LOGIC LEA200K Embedded Array Series Description The LEA200K Embedded Array Series is a submicron HCMOS ASIC product which com bines the integration and performance bene fits of Cell-Based ASICs with the fast turnaround time of Array-Based ASICs. The	OCR Scan	LEA200K 55-micron LCA200K 130 nm CMOS standard cell library 10-JK LEA100K CLDCC	PDF
pal16x4 Abstract: No abstract text available Text: 0257526 ADV M I C R O 96D P L A / P L E / ARRAYS 27109 D A rithm etic Series P A LI 6 X 4 • Bit-palr decoding ADV O rd erin g In fo rm atio n F e a tu re s /B e n e fits PAL16X4 C N STD • Easy generation of arithmetic operations D escrip tio n ARRAY INPUTS	OCR Scan	PAL16X4 T-46-13-47	PDF
PC8245 Abstract: No abstract text available Text: 3& ELW 5,6& ,QWHJUDWHG 3URFHVVRU DFW 6KHHW The PC8245 Integrated Processor implementing the PowerPC architecture fits applications where cost, space, power consumption, and performance are critical requirements. This device is designed to provide a high level of	Original	PC8245 32-bit 352-ball PCX8245 BP123	PDF
PAL16V8 Abstract: 16V8 18CV8 PEEL18CV8ZJ-25 PEEL18CV8ZP-25 PEEL18CV8ZS-25 PEEL18CV8ZJ25 PEEL18CV8ZP-25L Text: PEEL 18CV8Z -25 CMOS Programmable Electrically Erasable Logic Device Features Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA typical at standby - Icc = 2 mA (typical) at 1 MHz Architectural Flexibility - Enhanced architecture fits in more logic	Original	18CV8Z PAL16V8 16V8 18CV8 PEEL18CV8ZJ-25 PEEL18CV8ZP-25 PEEL18CV8ZS-25 PEEL18CV8ZJ25 PEEL18CV8ZP-25L	PDF
pal16v8 Abstract: dec mer PEEL18CV8ZP-25L Text: ic PEEL 18CV8Z -25 CMOS Programmable Electrically Erasable Logic Device Features Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA typical at standby - Icc = 2 mA (typical) at 1 MHz Architectural Flexibility - Enhanced architecture fits in more logic	Original	18CV8Z Pro1-9600 pal16v8 dec mer PEEL18CV8ZP-25L	PDF
82c11 Abstract: COM82C11 MOA4 m82c11 Text: COM82C11 STANDARD MICROSYSTEMS CORPORATION Æ PRELIMINARY Printer Adapter Interface PAI PIN CONFIGURATION FEATURES □ Fits Popular Centronics Printer Interface □ Programmable parallel printer interface □ Completely TTL-com patible I/O X, ( - • ■ ■ -e	OCR Scan	COM82C11 82c11 COM82C11 MOA4 m82c11	PDF
PEEL18CV8P-15 Abstract: PEEL18CV8S-7 Text: Not recommended for New designs contact factory for availability PEEL 18CV8 -7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array	Original	18CV8 25MHz PEEL18CV8P-15 PEEL18CV8S-7	PDF
PEEL18CV8P-15 Abstract: PEEL18CV8J-10 PEEL18CV8P 18CV8 PEEL18CV8P-25L PEEL18CV PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8P-25 PEEL18CV8J-7 Text: PEEL 18CV8 -7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array - 10 inputs and 8 I/O pins - 12 possible macrocell configurations	Original	18CV8 25MHz PEEL18CV8P-15 PEEL18CV8J-10 PEEL18CV8P PEEL18CV8P-25L PEEL18CV PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8P-25 PEEL18CV8J-7	PDF
Untitled Abstract: No abstract text available Text: Commercial/ Industrial INC. PEEL 18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features • - ■ Architectural Flexibility Multiple Speed Power, Temperature Options - Enhanced architecture fits in m ore logic - 74 product te rm s x 36 input AN D array	OCR Scan	18CV8 20-Pin 0001fl3fl 407D7	PDF
18CV8 Abstract: No abstract text available Text: Not recommended for New designs contact factory for availability PEEL 18CV8 -7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array	Original	18CV8 25MHz	PDF
tms320c5416 architecture diagram Abstract: CY4625 CY7C4625-15AC 8051 project report on traffic light controller TMS320C5416 manuals CY7C4265 CY7C4265-15AC TMS320C5416 external bus interfacing signals in tms320c5416 TI5416 Text: EZ-USB FX2 GPIF Primer Abstract This primer first introduces the underlying architecture of the EZ-USB® FX2™ before jumping into basic GPIF concepts, giving you a solid understanding of how the GPIF fits into the overall data path. A methodology is then presented for developing GPIF applications. This allows you to get a grasp of what the key pieces that	Original	GP2003. tms320c5416 architecture diagram CY4625 CY7C4625-15AC 8051 project report on traffic light controller TMS320C5416 manuals CY7C4265 CY7C4265-15AC TMS320C5416 external bus interfacing signals in tms320c5416 TI5416	PDF
vhdl code for deserializer Abstract: XAPP670 RocketIO ML321 RXRECCLK verilog code for fibre channel vhdl code for DCM Text: Application Note: Virtex-II Pro Family R XAPP670 v1.0 June 10, 2003 Summary Minimizing Receiver Elastic Buffer Delay in the Virtex-II Pro RocketIO Transceiver Author: Jeremy Kowalczyk This application note describes a design that reduces latency through the receive elastic buffer	Original	XAPP670 ML321 8B/10B 10-bit, 20-bit, 40-bit 8B/10B com/pub/applications/xapp/xapp670 vhdl code for deserializer XAPP670 RocketIO ML321 RXRECCLK verilog code for fibre channel vhdl code for DCM	PDF

Extended PCI Arbiter Abstract: PC8240 SDRAM controller 32bit 16MB Text: 3& ELW 5,6& ,QWHJUDWHG 3URFHVVRU DFW 6KHHW The PC8240 Integrated PowerPC Instruction Set Architecture ISA) processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of	Original	PC8240 PCX8240 BP123 Extended PCI Arbiter SDRAM controller 32bit 16MB	PDF
7 Series FPGAs GTP Transceivers User Guide, UG482 v1.5 Abstract: No abstract text available Text: 7 Series FPGAs GTP Transceivers User Guide UG482 v1.6 August 28, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL	Original	UG482 7 Series FPGAs GTP Transceivers User Guide, UG482 v1.5	PDF
powerpc dhrystone mips Abstract: MPC8240 The PowerPC Microprocessor Family Text: MPC8240FACT/D Fact Sheet MOTOROLA MPC8240 I N T E G R AT E D P O W E R P C P R O C E S S O R The MPC8240 Integrated PowerPC Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to	Original	MPC8240FACT/D MPC8240 MPC8240 powerpc dhrystone mips The PowerPC Microprocessor Family	PDF
circuit diagram for rogrammable logic controller Abstract: freescale 352 tbga MPC8240 Text: Freescale Semiconductor, Inc. Fact Sheet MPC8240 Freescale Semiconductor, Inc. INTEGRATED HOST PROCESSOR The MPC8240 Integrated Host Processor implementing the PowerPC architecture fits applications where cost, space, power consumption, and performance are critical	Original	MPC8240 MPC8240 MPC8240fact/rev circuit diagram for rogrammable logic controller freescale 352 tbga	PDF
MPC8240 Abstract: doorbell kb 10 Text: Fact Sheet MPC8240 INTEGRATED HOST PROCESSOR The MPC8240 Integrated Host Processor implementing the PowerPC architecture fits applications where cost, space, power consumption, and performance are critical requirements. This device provides a high level of	Original	MPC8240 MPC8240 MPC8240fact/rev doorbell kb 10	PDF
MPC8245 Abstract: No abstract text available Text: MPC8245 Motorola Integrated Host Processor The MPC8245 Integrated Host Typical Applications Processor implementing the PowerPC • Wireless LAN architecture fits applications where • Routers/Switches cost, space, power consumption and • Embedded Computing	Original	MPC8245 MPC8245	PDF
circuit diagram of wireless door BELL Abstract: internet controller door bell MPC8241 Text: Fact Sheet MPC8241 INTEGRATED HOST PROCESSOR The MPC8241 Integrated Host Processor implementing the PowerPC architecture fits applications where cost, space, power consumption, and performance are critical requirements. This device is designed to provide a high	Original	MPC8241 MPC8241 32-bit 64-bit MPC8241fact/rev circuit diagram of wireless door BELL internet controller door bell	PDF
S1C17564 Abstract: thyristor PSR 406 Text: CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17554/564 Technical Manual Rev.1.1 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability	Original	16-BIT S1C17554/564 S1C17564 thyristor PSR 406	PDF
MPC8241 Abstract: No abstract text available Text: MPC8241 Motorola Integrated Host Processor The MPC8241 Integrated Host Typical Applications Processor implementing the PowerPC • Wireless LAN architecture fits applications where • Routers/Switches cost, space, power consumption and • Embedded Computing	Original	MPC8241 MPC8241	PDF
MPC8245 Abstract: MPC8245FACT Text: Integrated Host Processors MPC8245 PowerPC Processor MPC8245 BLOCK DIAGRAM Overview The MPC8245 integrated host processor Message Controller I2C PLL ® implementing the PowerPC architecture fits I2 C requirements. This device is designed to provide a high level of integration, reducing chip count	Original	MPC8245 MPC8245 MPC8245FACT MPC8245FACT	PDF

CLOCK BUFFER FITS Search Results

CLOCK BUFFER FITS Result Highlights (5)

CLOCK BUFFER FITS Datasheets Context Search

CY7B185

A1280A VKS

LCA200K

pal16x4

PC8245

PAL16V8

pal16v8

82c11

PEEL18CV8P-15

PEEL18CV8P-15

Untitled

18CV8

tms320c5416 architecture diagram

vhdl code for deserializer

Extended PCI Arbiter

7 Series FPGAs GTP Transceivers User Guide, UG482 v1.5

powerpc dhrystone mips

circuit diagram for rogrammable logic controller

MPC8240

MPC8245

circuit diagram of wireless door BELL

S1C17564

MPC8241

MPC8245