CL2C12 Search Results

Contextual Info: SGS-THOMSON ST90E27/T27 ST90E28/T28 M S ^ ( g [l^ ( O T ® iQ S 16K EPROM HCMOS MCUs WITH RAM Register oriented 8/16 bit CORE with RUN, WFI and HALT modes Minimum instruction cycle time: 500ns (12MHz internal) Internal M em ory: EPROM 16Kbytes RAM

Contextual Info: MOSEL VITELIC V53C16129H HIGH PERFORMANCE 128K X 16 BIT EDO PAGE MODE CMOS DYNAMIC DRAM PRELIMINARY 40 45 50 60 Max. RAS Access Time, tRAC 40 ns 45 ns 50 ns 60 ns Max. Column Address A ccess Tim e, (tc/vO 20 ns 22 ns 24 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tPC)

53C104D

Contextual Info: M O S E L VTTEUC V53C104D HIGH PERFORMANCE, LOW POWER 256K X 4 B IT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 60 70 80 Max. RAS Access Time, tFiAC 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns 40 ns Min. Fast Page Mode Cycle Time, (tp c )

Contextual Info: N N 5 1 V 1 6 1 6 5 A / N N 5 1 V 1 8 1 6 5 A E D O s e r ie s H y p e r P a g e M o d e C M O S 1M x x N P N w i W l 1 6 b it D y n a m ic R A M Preliminary Specification d e s c rip tio n The NN51V16165A/18165A series is a high performance CMOS Dynamic Random Access Memory orga­

CL2C12

Contextual Info: MOSEL- VITELIC V53C100N HIGH PERFORMANCE, 3.3 VOLT 1 M X 1 B IT FA ST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE V53C100N 60/60L PRELIMINARY 70/70L 80/80L Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 35 ns 40 ns 45 ns

Contextual Info: M54HC137 M74HC137 SGS-THOMSON * 5 7 M 3 TO 8 LINE DECODER/LATCH INVERTING • HIGHSPEED tpD = 11 ns (TYP.) AT Vcc = 5 V . LOW POWER DISSIPATION Icc = 4 (iA (MAX.) AT Ta = 25 °C ■ HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY

Contextual Info: M O S E L V iT E U C V53C181608 1M X 16 PAGE MODE CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT HIGH PERFORMANCE 50 60 70 50 ns 60 ns 70 ns Max. Column Address Access Time, tCAA 25 ns 30 ns 35 ns Min. Extended Data Out Page Mode Cycle Time, (tPC) 20 ns 25 ns