CE1X Search Results

ras 0610 relay

Abstract: relay sm1 SH7712 RBL 43 P 530 SE SH7710 S273S
Contextual Info: User's Manual 32 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7710, SH7712, SH7713 Group User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

CE1X

Abstract: fast sram 100mhz CE2Y GALVANTECH
Contextual Info: ADVANCE INFORMATION GALVANTECH, INC. DUAL I/O DUAL ADDRESS SYNCHRONOUS SRAM GVT81256P36/GVT81128P36 256K/128K X 36 PIPELINED SRAM 256K/128K X 36 SRAM +3.3V SUPPLY, FULLY REGISTERED TWO BI-DIRECTIONAL DATA BUSES FEATURES GENERAL DESCRIPTION • • • •

A12L

Abstract: A14L IDT70V3579 IDT70V3579S
Contextual Info: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 5/6ns max. Pipelined output mode

A14L

Contextual Info: HIGH-SPEED 32K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM PRELIMINARY IDT70927S/L Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simultaneous access of the same memory location • High-speed clock to data access — Commercial: 20/25/30ns

70v3319s133

Abstract: 70V3319 A12L IDT70V3319 IDT70V3319S 70V3319S 70V3319PRF
Contextual Info: HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3319S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

70V3569

Abstract: A12L A13L IDT70V3569 IDT70V3569S
Contextual Info: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3569S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access

A14L

Abstract: IDT70V9279 IDT70V9279L IDT70V9279S
Contextual Info: HIGH-SPEED 3.3V 32K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9279S/L Integrated Device Technology, Inc. FEATURES: • Full synchronous operation on both ports - 4ns setup to clock and 1ns hold on all control, data, and address inputs

A12L

Abstract: A15L A15R
Contextual Info: PRELIMINARY IDT70V908S/L HIGH-SPEED 3.3V 64K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simultaneous access of the same memory location • High-speed clock to data access

PIR alarm system

Abstract: txal* 228 bs ADE-602-096B dp83848 application 264 bf BT 816 cd0a2 un 816 i 336 SH7700 DP83848
Contextual Info: REJ09B0288-0150 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7713 32 Hardware Manual TM SuperH

txal* 228 bs

Abstract: CD 5888 CB CD 5888 BU 808 DX 851 A24 h2a SH7712 cd0a2 DST 09 PFC1 Nippon capacitors bcd to seven segment circuit diagram
Contextual Info: REJ09B0269-0100 SH7712 32 Hardware Manual TM SuperH Renesas 32-Bit RISC Microcomputer RISC engine Family / SH7700 Series SH7712 Rev.1.00 Revision Date: Dec. 27, 2005 HD6417712 Rev. 1.00 Dec. 27, 2005 Page ii of xlii Keep safety first in your circuit designs!

mt 1389 de

Abstract: 1838 b infrared Schematics AL 1450 DV stc 1740 relay ras 1210 1838 t infrared cd 1619 CP bt 1690 scr pin diagram for IC cd 1619 cr tea 1601
Contextual Info: REJ09B0256-0100 32 SH7763 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series R5S77630 Rev.1.00 Revision Date: Oct. 01, 2007 Rev. 1.00 Oct. 01, 2007 Page ii of lxvi Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate

4848

Abstract: A12L A13L A14L A15L A15R IDT709189 IDT709189L
Contextual Info: PRELIMINARY IDT709189L HIGH-SPEED 64K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 7.5/9/12ns max.

A13L

Abstract: IDT709269 IDT709269S
Contextual Info: PRELIMINARY IDT709269S/L HIGH-SPEED 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9/12/15ns max.

A15L

Abstract: A15R IDT70V9289 IDT70V9289L wl 1281
Contextual Info: PRELIMINARY IDT70V9289L HIGH-SPEED 3.3V 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 7.5/9/12ns max.

Contextual Info: IDT70V9169/59L HIGH-SPEED 3.3V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9ns max.

4844

Contextual Info: IDT709389L HIGH-SPEED 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 7.5/9/12ns max.

tdc 310

Abstract: ba6l BA6R 10 35L U1
Contextual Info: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip

TSB 36

Contextual Info: HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT70V9269S/L Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9/12/15ns max.

ba6l

Contextual Info: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks – 2 megabits of memory on chip

A12L

Abstract: A13L A15L A15R g8434 tdc3200
Contextual Info: PRELIMINARY IDT70908S/L HIGH-SPEED 64K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 20/25/30ns max.

A14L

Abstract: IDT70V9279 IDT70V9279L IDT70V9279S
Contextual Info: PRELIMINARY IDT70V9279S/L HIGH-SPEED 3.3V 32K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9/12/15ns max.

IDT70T659

Contextual Info: HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port

70V3319

Abstract: A12L IDT70V3319 IDT70V3319S L1 ORT X
Contextual Info: HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3319S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

10 35L U4

Abstract: 70V7589 IDT70V7589 IDT70V7589S BA5L
Contextual Info: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7589S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks