CD54AC00F3A Search Results

Contextual Info: CD54A C00F3A, CD54ACT00F3A I ia t t r i- * * « S E M I C O N D U C T O R Quad 2-Input NAND Gate July 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conform ant Under the Provisions of Paragraph 1.2.1. The CD54AC00F3A and CD54ACT00F3A are quad 2-input

JM38510

Abstract: JM38510/05202BCA 54FCT540DMQB 54ACT00DMQB Mil JAN jm38510 Cross Reference national semiconductor cmos JM38510/05302 54ACT374DMQB JM38510-05003BCA 7704601CA
Contextual Info: Harris Semiconductor to National Semiconductor CMOS DIGITAL CROSS-REFERENCE GUIDE REV. 12/98 Harris Part # CD54AC00F3A CD54AC02F3A CD54AC04F3A CD54AC05F3A CD54AC08F3A CD54AC109F3A CD54AC138F3A CD54AC139F3A CD54AC153F3A CD54AC157F3A CD54AC161F3A CD54AC163F3A

CD54ACT00F3A

Abstract: CD54AC00F3A
Contextual Info: CD54AC00F3A, CD54ACT00F3A Semiconductor Quad 2-Input NAND Gate July 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The CD54AC00F3A and CD54ACT00F3A are quad 2-input

AC00

Abstract: CD54AC00 CD54AC00F3A CD74AC00 CD74AC00E CD74AC00M CD74AC00M96
Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

AC00

Abstract: CD54AC00 CD54AC00F3A CD74AC00 CD74AC00E CD74AC00M CD74AC00M96
Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

AC00

Abstract: CD54AC00 CD54AC00F3A CD74AC00 CD74AC00E CD74AC00M CD74AC00M96
Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCHS303 – JANUARY 2001 D AC Types Feature 1.5-V to 5.5-V Operation D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar FCT, AS, and S, With

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303A – JANUARY 2001 – REVISED MARCH 2001 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

74ACT00 HARRIS

Abstract: SCHS223 AC00 CD54AC00F3A CD54ACT00F3A CD74AC00E CD74AC00M CD74ACT00E 2B54B
Contextual Info: CD54/74AC00, CD54/74ACT00 Data sheet acquired from Harris Semiconductor SCHS223A Quad 2-Input NAND Gate September 1998 - Revised June 2000 Features Description • Typical Propagation Delay - 3.2ns at VCC = 5V, TA = 25oC, CL = 50pF The ’AC00 and ’ACT00 are quad 2-input NAND gates that utilize the Advanced CMOS Logic technology.

JM38510/01405BEA

Abstract: EPROM databook AMD pcb repair 54AC299 5962-8961501QXA 5962-8961501VPA DS16F95 DS16F95J-QMLV JM38510 54AC273DMQB
Contextual Info: N VOLUME NO. 16 1999 1999 WILL HAVE MANY CHALLENGES A s we enter 1999, the many changes that started in the Military/Aerospace market over the past few years continue unabated. Driven by the need to use the latest technology and the government’s initiative to reduce the acquisition cost of equipment, we have seen:

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

CD54AC00

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54A C00F3A, CD54ACT00F3A ¡ - i^ p p ia S E M I C O N D U C T O R July 1998 Q u ad 2 -In p u t N A N D G a te Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.

CD54AC00

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

MILITARY

Abstract: 5962-8755201RA 59628762201EA 5962-8766301RA
Contextual Info: Military and Aerospace DE8C Standard Military Drawing Cross-Reference Guide BY STANDARD MILITARY DRAWING NUMBER BY RCA DEVICE TYPE STANDARD MILITARY DRAWING # RCA DEVICE RCA DEVICE STANDARD MILITARY

Contextual Info: CD54AC00, CD74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS303C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC00 . . . F PACKAGE CD74AC00 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

ACT00

Abstract: AC00 74ACT00 HARRIS
Contextual Info: CD54/74AC00, CD54/74ACT00 Data sheet acquired from Harris Semiconductor SCHS223A Quad 2-Input NAND Gate September 1998 - Revised June 2000 Features Description • Typical Propagation Delay - 3.2ns at VCC = 5V, TA = 25oC, CL = 50pF The ’AC00 and ’ACT00 are quad 2-input NAND gates that utilize the Advanced CMOS Logic technology.