C100E Search Results

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual D ifferential PECL to TTL Translator M C100ELT23 The C100ELT23 is a dual differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual gate

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 M C100E195 Program m able Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay ot a differential ECL input transition.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6-Bit Universal Up/Down Counter M C10E136 M C100E136 The MC1OE/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cacading

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple D Flip-Flop With Set and Reset MC100LVEL30 M C100EL30 The MC100LVEL30 is a triple master-slave D flip flop with differential outputs. The C100EL30 is pin and functionally equivalent to the MC100LVEL30 but is specified for operation at the standard 100E ECL

LC313

Contextual Info: MOTOROLA SEM ICONDUCTO R TECHNICAL DATA 6-Bit D Latch M C10E150 M C100E150 The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A

Contextual Info: MOTOROLA SEM ICO N D U CTO R bflE ]> • b 3 b ? S S E GD'lSDfia THE M O T O R O L A SC TECHNICAL DATA Product Preview Dual T T L to Differential E C L Translator i nom L O G I C 1 M C10ELT24 M C100ELT24 The MC10ELT/100ELT24 is a TTL to differential E C L translator.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C10EL05 M C100EL05 2 -ln p u t D iffe re n tia l A N D /N A N D The MC1OEL/100EL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the E404 device with higher performance capabilities.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information MC100LVEL56 M C100EL56 Dual Differential 2:1 M ultiplexer The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The C100EL56 is pin and functionally equivalent to the MC100LVEL56 but is specified for operation at the standard 100E ECL voltage supply. The

MC100EL35

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA JK Flip-Flop M C10EL35 M C100EL35 The M C10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.

KPT23

Contextual Info: C100EPT23 Dual Differential LVPECL to LVTTL Translator The M C100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive EC L levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for

Contextual Info: MOTO RO LA °rderNum berR “„c:°” Semiconductor Components M C100EPT24 SO -8, D SUFFIX 8 - L E A D P L A S T IC S O IC P A C K A G E C A S E 751 ORDERING INFORMATION M C 100E PT24D S O IC Product Preview LVTTL/LVCMOS to D ifferential LVECL Translator

MC100EL32

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA h-2 Divider M C10EL32 M C100EL32 The MC10EL/100EL32 is an integrated - 2 divider. The differential clock inputs and the V b b allow a differential, single-ended or AC coupled interface to the device. If used, the V b b output should be bypassed to

MC100EL32

Contextual Info: MOTOROLA SEM ICONDUCTO R TECHNICAL DATA 2 Divider M C10EL32 M C100EL32 The M C 1 0 E L / 1 0 0 E L 3 2 is an integrated +2 divider. T he differential clock inputs an d the V b b allow a differential, single-ended or A C coupled interface to the device. If used, the V b b output should be b y p a sse d to

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA P roduct Preview Low Voltage 2:8 Differential Fanout Buffer M C100E310 ECL/PECL Com patible For inform ation on the C100E310, please refer to the MC100LVE310 datasheet on p a g e 4 -1 4 in C hapter 4 o f this book. LOW VOLTAGE

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 1:2 Fanout D ifferen tial PECL to TTL Translator M C10ELT26 M C100ELT26 The MC10ELT/100ELT26 is a 1:2 fanout differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3 -B it 4:1 M u x -L a tc h T h e M C 1 0 E /1 0 0 E 1 5 6 c o n ta in s th re e 4:1 M C10E156 M C100E156 m u ltip le x e rs fo llo w e d by tra n s p a re n t la tc h e s w ith d iffe re n tia l o u tp u ts . W h e n b o th L a tc h E n a b le s

MAX4242

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1:5 Clock Distribution Chip M C100LVEL14 M C100EL14 The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage Dual 1 ¡4, 1:5 Differential Fanout Buffer M C100E210 ECL/PECL Compatible For inform ation on the C100E210, please refer to the MC100LS/E210 datasheet on p a g e 4 -7 in C hapter 4 o f this book. LOW VOLTAGE

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 M C100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

Contextual Info: MOTOROLA bflE » SEMICONDUCTOR b 3 b ? E 5 2 D G T H T S E blT I ¡M0TM M O TO RO LA SC LOGI C I TECHNICAL DATA 3-Bit 4:1 Mux-Latch MC10E156 M C100E156 The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. W hen both Latch Enables

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview +214, 4/5/6 C lock M C100EP39 G eneration Chip The C100EP39 is a low skew +2/4, +4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

KPT22

Abstract: C100EPT22
Contextual Info: M C 100EP T22 Dual LVTTL/LVCMOS to D ifferen tial LVPECL T ran slator The M C100EPT22 is a dual LVTTL/LVCM OS to differential LVPECL translator. Because LVPECL Positive EC L levels are used only +3.3V and ground are required. The small outline 8-lead SOIC

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 4-Bit Parallel/Serial Converter MC10E446 M C100E446 The MC10E/100E446 is an integrated 4-bit parallel to serial data converter. The device is designed to operate for NRZ data rates of up to 1.3Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1:4 C lock D istribution Chip M C10EL15 M C100EL15 The MC10EL7100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if