C10E156 Search Results

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3 -B it 4:1 M u x -L a tc h T h e M C 1 0 E /1 0 0 E 1 5 6 c o n ta in s th re e 4:1 M C10E156 M C100E156 m u ltip le x e rs fo llo w e d by tra n s p a re n t la tc h e s w ith d iffe re n tia l o u tp u ts . W h e n b o th L a tc h E n a b le s

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C10E156 M C 100E156 950 ps Max. D to O utput 850 ps Max. LEN to O utput D ifferential O utputs A synchronous M aster Reset Dual Latch-Enables Extended 100E Vgg Range o f - 4 .2 V to 75 k il Input P ulldow n Resistors

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3-Bit 4:1 Mux-Latch M C10E156 M C100E156 The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3-Bit 4:1 M ux-Latch M C10E156 M C100E156 The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3-Bit 4:1 Mux-Latch C10E156 MC100E156 The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is