Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    BUS ATA Search Results

    BUS ATA Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TUSB9261IPAPRQ1 Texas Instruments Automotive 2nd Generation SuperSpeed USB 3.0 to Serial ATA Bridge 64-HTQFP -40 to 85 Visit Texas Instruments Buy
    TUSB6250PFC Texas Instruments USB 2.0 Low-Power, High-Speed ATA/ATAPI Bridge Solution 80-TQFP 0 to 70 Visit Texas Instruments Buy
    TUSB9261IPAPQ1 Texas Instruments Automotive 2nd Generation SuperSpeed USB 3.0 to Serial ATA Bridge 64-HTQFP -40 to 85 Visit Texas Instruments Buy
    CS-SATDRIVEX2-001 Amphenol Cables on Demand Amphenol CS-SATDRIVEX2-001 Serial ATA Extension Cable - SATA II Drive Extension Cable with Power (6.0 Gbps) 1m Datasheet
    CS-SATDRIVEX2-002 Amphenol Cables on Demand Amphenol CS-SATDRIVEX2-002 Serial ATA Extension Cable - SATA II Drive Extension Cable with Power (6.0 Gbps) 2m Datasheet

    BUS ATA Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: HT-1000 I/O CONTROLLER SUMMARY OF BENEFITS FEATURES • The HT-1000 integrates: • 8x HyperTransport bus • Integrated South Bridge • PCI-X 64 bus/133 bus • PCI 32 bus/33 bus • Four-port SATA II • Four-port USB 2.0 • Single-channel ATA 100 IDE


    Original     		PDF HT-1000 HT-1000 bus/133 bus/33 HT-1000-PB01-R

    HT1000

    Abstract: HT-1000 pci-e sata bridge controller HT-2000
    Text: HT-1000 I/O CONTROLLER FEATURES • The HT-1000 integrates: • • • • • • • • • • • • 8x HyperTransport bus Integrated South Bridge PCI-X® 64 bus/133 bus PCI 32 bus/33 bus Four-port SATA II Four-port USB 2.0 Single-channel ATA 100 IDE


    Original     		PDF HT-1000 HT-1000 bus/133 bus/33 HT-1000-PB02-R HT1000 pci-e sata bridge controller HT-2000

    05207-SB-FINAL

    Abstract: WISTRON power sequence wistron Wistron Corporation SPRING, COIL, 17-7 SST C562E ATD97SC3203 R5C811 DC100V1 yonah calistoga ICH7-M UltraBay
    Text: July 22 '05 Intel Yonah NV/LV/ULV Processor 3,4,5 Clock Generator CK-410M 19 AGTL+ FSB Thermal Sensor LM26 I2C Bus / SM Bus Bus Switch IC 54 SATA HDD CRT I/F 8,9,10,11,12,13,14 Board to Board CONN 44 Intel ICH7-M Serial ATA I/F Port 0 PCI Bus / 33MHz SD Socket


    Original     		PDF CK-410M 533/667MHz 05207-SB-FINAL 200-PIN 400/533/667MHz MAX1989 49U25 SPRING-31-GP 49U24 05207-SB-FINAL WISTRON power sequence wistron Wistron Corporation SPRING, COIL, 17-7 SST C562E ATD97SC3203 R5C811 DC100V1 yonah calistoga ICH7-M UltraBay

    vqfp package pinout

    Abstract: PCMCIA Z16017 z53c8003fsc 100-Pin Package Pin-Out Diagram scsi evaluation board
    Text: Mass Storage Bus Interface Zilog Superintegration Pr oducts Guide PCMCIA Bus Z16017 Block Diagram Address Decoder Window Decoder Five Configuration Registers Peripheral PCMCIA Bus Bus Peripheral Bus I/F 16-Bit Address Decoder Window Decoder Five Configuration


    Original     		PDF Z16017 16-Bit) Z16017/Z16M17 Z86017/Z86M17 16-Bit Z53C8003FSC1746 Z6017 100-Pin vqfp package pinout PCMCIA Z16017 z53c8003fsc 100-Pin Package Pin-Out Diagram scsi evaluation board

    G78F

    Abstract: No abstract text available
    Text: External Bus 1 This chapter describes the bus interface of the i960 Jx processor. It explains the following: • • • • Bus states and their relationship to each other Bus signals, which consist of address/data, control/status Read, write, burst and atomic bus transactions


    Original     		PDF 8/16/32-bit) 80960Jx G78F

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74LS645 Octal Bus Transceivers General Description Features These octal bus transceivers are designed fo r asynchronous tw o-w ay com m unication between d ata buses. The devices transm it d ata from the A bus to the B bus or from the B bus


    OCR Scan     		PDF DM74LS645 20-pin DS009056on

    BUS65112

    Abstract: flatpack 48 v 65112
    Text: 000 BUS-65112 AND BUS-65117 ' ILC D ATA D E V IC E C O R P O R A T IO N !_ MIL-STD-1553 DUAL REDUNDANT REMOTE TERMINAL HYBRID FEATURES • SMALL SIZE & LOW POWER • COMPLETE RTU PROTOCOL BUS-65112 DDIP BUS-65117 FLATPACK DESCRIPTION The BUS-65112 is a com plete dual


    OCR Scan     		PDF BUS-65112 BUS-65117 MIL-STD-1553 BUS-65117 BUS65112 flatpack 48 v 65112

    DM54ALS640AJ

    Abstract: DM74ALS DM74ALS640AN DM74ALS640AWM J20A
    Text: DM54ALS640A/DM74ALS640A Inverting Octal Bus Transceivers General Description Features These inverting octal bus transceivers are designed for asynchronous two-way communication between data bus­ ses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level


    OCR Scan     		PDF DM54ALS640A/DM74ALS640A DM54ALS640A DM74ALS640A DM54ALS640AJ DM74ALS DM74ALS640AN DM74ALS640AWM J20A

    center tap transformer

    Abstract: No abstract text available
    Text: 000 BUS-65529 ILC DATA OKVICB CORPORATION_ & MIL-STD-1553 BC/RT/MT IBM PC/AT INTERFACE UNIT FEATURES DESCRIPTION The BUS-65529 provides full, intel­ ligent interfacing between a dual redun­ dant MIL-STD-1553B D ata Bus and the IBM PC/AT Bus. Software controls the


    OCR Scan     		PDF BUS-65529 MIL-STD-1553 1553B BUS-65529 MIL-STD-1553B S-65529 center tap transformer

    BUS-61553

    Abstract: BUS61553 bu-61553
    Text: 000 BUS-61553 ILC D ATA D EV ICE C O R P O RATION'S_ _ MIL-STD-1553 ADVANCED INTEGRATED MUX AIM HYBRID DESCRIPTION FEATURES DDC's BUS-61553 Advanced Integrated Mux (AIM) Hybrid is a complete MIL-STD-1553 Bus Controller (BC), Remote Terminal Unit (RTU), and Bus Monitor (MT)


    OCR Scan     		PDF BUS-61553 MIL-STD-1553 BUS-61553 78-pin MIL-STD-1553-to-host BUS-63102-Call BUS61553 bu-61553

    Untitled

    Abstract: No abstract text available
    Text: ^ 001 4, x y BUS-65610 _ ILC DATA DEVICE CORPORATION_ _ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR FEATURES DESCRIPTION The BUS-65610 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller BC , Remote Terminal Unit (RTU) and Bus Monitor (MT). Packaged


    OCR Scan     		PDF BUS-65610 MIL-STD-1553 BUS-65610 BUS-63125, BUS-65600 BUS-65612

    BUS-66300

    Abstract: No abstract text available
    Text: QQQ BUS-66312 ILC D ATA D E V IC E CO RPO RATIO N _ MIL-STD-1553 TO MICROPROCESSOR INTERFACE UNIT REFER TO BUS-61553 FOR MEMORY MANAGEMENT DESCRIPTION AND TIMING. DESCRIPTION DDC's BUS-66312 M IL-S TD -1553 to M icroprocessor Interface Unit sim plifies the CPU to 1553 Data Bus interlace


    OCR Scan     		PDF BUS-66312 MIL-STD-1553 BUS-61553 BUS-66312 VII-226 BUS-66312-883B MIL-STD-883 BUS-66300

    4038X

    Abstract: BUS-27765 BUS-65201 590i4 A5690 BUS-65101 BUS-66106 BUS-66111
    Text: 0 0 BUS-661068a n d BUS-66111 ILC DATA DEVICE CORPORATION MIL-STD-1553 BUS CONTROLLER PROTOCOL HYBRIDS BUS-66106 FEATURES • GENERATES PROTOCOL, TIMING AND CONTROL FOR MIL-STD-1553 OR MACAIR A5690 BUS CONTROLLER • SUPPORTS ALL MESSAGE FORMATS DESCRIPTION


    OCR Scan     		PDF BUS-661068and BUS-66111 BUS-66106 BUS-66106 BUS-66111 MIL-STD-1553 A5690. BUS-66111-883B 4038X BUS-27765 BUS-65201 590i4 A5690 BUS-65101

    DM74ALS

    Abstract: DM74ALS645A DM74ALS645AN DM74ALS645AWM 1524D
    Text: S E M IC O N D U C T O R tm DM74ALS645A Octal Bus Transceivers General Description These octal bus transceivers are designed for asynchronous tw o-w ay com m unication between data busses. These d e ­ vices transm it d ata from the A bus to the B bus or from th e B


    OCR Scan     		PDF DM74ALS645A DM74ALS645AN DM74ALS DM74ALS645AWM 1524D

    2T17

    Abstract: cdp1806ac GEC 44 3A CDP1805 CDP1805ACE p1806 k4080 1806AC
    Text: G E SOLID STATE 01 i>Ë| 3Û7SDÛ1 QDlbDÛD _ 1800-Series Microprocessors and Microcomputers TERMINAL ASSIGNMENT CLOCK — WAIT -ÊL6ÏS — 0 — SCI — SCO — B7T5 — eus 7 — BUS 6 — BUS 3 — BUS 4 — BUS 3 — BUS 2 — BUS 1 — BUSO —


    OCR Scan     		PDF 1800-Series C0PI80 92CS-3S0C4 CDP1805AC, CDP1806AC 2T17 GEC 44 3A CDP1805 CDP1805ACE p1806 k4080 1806AC

    bck-01

    Abstract: RTU A08 BCK01 ILC Data Device 65610 65611 mcl d01 BUS-65600 A09 N03 BUS-65610
    Text: □01 4, > 7 BUS-65610 _ ILC DATA DEVICI CORPORATION_ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR APPROX. Vs ACTUAL SIZE FEATURES • DESCRIPTION The BUS-65610 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller BC , Remote Terminal Unit


    OCR Scan     		PDF BUS-65610 MIL-STD-1553 BUS-65610 BUS-63125, BUS-65600 BUS-65612 bck-01 RTU A08 BCK01 ILC Data Device 65610 65611 mcl d01 A09 N03

    1S2074

    Abstract: 74LSOO HD74LS640 AL667
    Text: • Octal Bus Transceivers inverted 3-state outputs Th is octal bus transceivers is designed for asynchronous two-way com m unication between data buses. Th e device transmit data from the A bus to the 6 bus or from the B bus to the A bus depending upon the level at the direction control (D IR ) input.


    OCR Scan     		PDF QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 1S2074 74LSOO HD74LS640 AL667

    CY54FCT646ATDMB

    Abstract: FCT646T CY54FCT
    Text: CY54/74FCT646T CY54/74FCT648T CYPRESS □P BA SAB Real-Time Transfer bus A to bus b Real-Time Transfer Bus B to Bus A CPA6 X H or L Transfer Stored Data to A and/or B Storage from A and/or B Function Table!2! D ata I /O ^ l Inputs O p era tio n or F u n ction


    OCR Scan     		PDF CY54/74FCT646T CY54/74FCT648T FCT646T or24-Lead 300-Mil) CY54FCT( 24-Lead CT648CT 28-Square CY54FCT646ATDMB CY54FCT

    sirio

    Abstract: MC3447
    Text: —228 — Bidirectional Bus G P IB Transceiver ^ Vcc ★ 3 X f — r Ih/j 23] b u s o n] bus l ( DATA) ★ U ] BUS 2 2D] BUS 3 ir — ~f y BUS 5 17] S/FÜ1-4) J6] BUS 6 l5] BUS 7 ] 3 T Y P IC A L R EC EIVE R — M 3.0 > 2.0 8_J O f- H Y STER ESIS 1 ' Vcc=5.0V


    OCR Scan     		PDF MC3447 sirio MC3447

    80960MC

    Abstract: FF000000 programmers reference manual
    Text: The 80960MC Processor and the Local Bus 3 CHAPTER 3 THE 80960MC PROCESSOR AND THE LOCAL BUS The 32-bit multiplexed local bus L-bus connects the 80960MC processor to memory and I/O and forms the backbone of any 80960MC processor based system. This high bandwidth bus provides


    OCR Scan     		PDF 80960MC 32-bit FF000000 programmers reference manual

    BUS65112

    Abstract: No abstract text available
    Text: 0Q Q ILC DATA D E V IC I CORPORATION _ BUS-65112 AND BUS-65117 MIL-STD-1553 DUAL REDUNDANT REMOTE TERMINAL HYBRID FEATURES • SMALL SIZE & LOW POWER • COMPLETE RTU PROTOCOL BUS-65112 DDIP BUS-65117 FLATPACK DESCRIPTION The BUS-65112 is a com plete dual


    OCR Scan     		PDF BUS-65112 BUS-65117 MIL-STD-1553 BUS-65117 12MHz 1801A BUS65112

    5A5B

    Abstract: No abstract text available
    Text: HD 74LS640. O ctal Bus Transceivers inverted 3-s ta te outputs This octal bus transceivers is designed fo r asynchronous tw o -w ay co m m unicatio n betw een data buses. IPIN ARRANGEMENT T h e device transm it data fro m th e A bus to th e 8 bus or fro m th e B bus t o th e A bus


    OCR Scan     		PDF HD74LS640 T-90-10 ib203 5A5B

    MC68340

    Abstract: No abstract text available
    Text: SECTION 3 BUS OPERATION This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt condi­ tions, bus arbitration, and reset operation. Operation of the external bus is the same whether


    OCR Scan     		PDF MC68340 16-bit MC68340KIN SIM40

    Untitled

    Abstract: No abstract text available
    Text: D _ DC i/:'1! Z,W ; VJ«- BUS-65612 ILC DATA DEVICE CORPORATION _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACT FACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION The BUS-65612 is a 16 MHz single chip dual re dund ant M IL-S TD -1553 Bus


    OCR Scan     		PDF BUS-65612 MIL-STD-1553 BUS-65612 MIL-STD-1553 BUS-63125, BUS-65600 -3/92-1M