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    BURST BUS MODE Search Results

    BURST BUS MODE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    FO-9LPBMTRJ00-001 Amphenol Cables on Demand Amphenol FO-9LPBMTRJ00-001 MT-RJ Connector Loopback Cable: Single-Mode 9/125 Fiber Optic Port Testing .1m Datasheet
    CS-USB3.1TYPC-001M Amphenol Cables on Demand Amphenol CS-USB3.1TYPC-001M Amphenol Premium USB 3.1 Gen2 Certified USB Type A-C Cable - USB 3.0 Type A Male to Type C Male [10.0 Gbps SuperSpeed] 1m (3.3ft) Datasheet
    CS-USBAM003.0-001 Amphenol Cables on Demand Amphenol CS-USBAM003.0-001 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-A Cable - USB 3.0 Type A Male to Type A Male [5.0 Gbps SuperSpeed] 1m (3.3') Datasheet
    CS-USBAB003.0-002 Amphenol Cables on Demand Amphenol CS-USBAB003.0-002 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-B Cable - USB 3.0 Type A Male to Type B Male [5.0 Gbps SuperSpeed] 2m (6.6') Datasheet
    CS-USBAB003.0-001 Amphenol Cables on Demand Amphenol CS-USBAB003.0-001 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-B Cable - USB 3.0 Type A Male to Type B Male [5.0 Gbps SuperSpeed] 1m (3.3') Datasheet

    BURST BUS MODE Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Motorola MPC556

    Abstract: MPC556 Motorola 417 0C00 1C00 MPC555 0x80E0 branch conditional unconditional instruction
    Text: SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order


    Original     		MPC556. MPC556 MPC555 MPC556 Motorola MPC556 Motorola 417 0C00 1C00 0x80E0 branch conditional unconditional instruction PDF

    Motorola MPC556

    Abstract: 0C00 1C00 MPC555 MPC556 Motorola 417 "Huffman coding" branch conditional unconditional instruction
    Text: SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order


    Original     		MPC556. MPC556 MPC555 MPC556 Motorola MPC556 0C00 1C00 Motorola 417 "Huffman coding" branch conditional unconditional instruction PDF

    0x802c

    Abstract: 0x00E00 SRR10 0x8074 0C00 1C00 MPC555 0x8070 0x01d00
    Text: SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order


    Original     		32Kbytes. MPC555 0x802c 0x00E00 SRR10 0x8074 0C00 1C00 MPC555 0x8070 0x01d00 PDF

    diode BBC

    Abstract: 0x80E0 0C00 1C00 MPC555
    Text: SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order


    Original     		32Kbytes. MPC555 diode BBC 0x80E0 0C00 1C00 MPC555 PDF

    PC107A

    Abstract: microprocessor PC107
    Text: PC107A PCI Bridge Memory Controller Datasheet Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1


    Original     		PC107A 32-bit 0842E PC107A microprocessor PC107 PDF

    4082

    Abstract: c 4082 PBSRAM ci 4082
    Text: PRELIMINARY IDT7MBV4150 IDT7MBV4151 IDT7MBV4152 128K x 64/256K x 72 SYNCHRONOUS PIPELINED BURST SRAM 256K x 72 BURST ZBT SRAM MODULE FAMILY FEATURES: DESCRIPTION: • Pin compatible module family for pipelined burst SRAM and pipelined burst zero bus turnaround ZBT™ SRAM


    Original     		IDT7MBV4150 IDT7MBV4151 IDT7MBV4152 64/256K 160-lead 66MHz, IDT7MBV4150/51/52 7MBV4150 7MBV4151 7MBV4152 4082 c 4082 PBSRAM ci 4082 PDF

    T25 4 F8

    Abstract: PC7400 ATMEL 744 MPC107 PC107A PCX107A
    Text: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible


    Original     		32-bit 2137D PC107A T25 4 F8 PC7400 ATMEL 744 MPC107 PC107A PCX107A PDF

    MPC107

    Abstract: PC107A PC7400 atmel 458
    Text: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible


    Original     		32-bit 2137D PC107A MPC107 PC107A PC7400 atmel 458 PDF

    MPC107

    Abstract: PC107A PC7400
    Text: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible


    Original     		32-bit 2137D MPC107 PC107A PC7400 PDF

    TMs 1122

    Abstract: No abstract text available
    Text: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible


    Original     		32-bit 2137D TMs 1122 PDF

    a23 862-1

    Abstract: T25 4 h5 ATMEL 744 W6 13A Diode atmel 718 atmel 819 diode t25 4 E5 diode t25 4 L5 IN5820 military standard mpc107
    Text: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible


    Original     		32-bit 2137C a23 862-1 T25 4 h5 ATMEL 744 W6 13A Diode atmel 718 atmel 819 diode t25 4 E5 diode t25 4 L5 IN5820 military standard mpc107 PDF

    diode t25 4 F8

    Abstract: military standard mpc107 MPC107 PC107A PC7400 transistor pc107
    Text: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0 V Compatible


    Original     		32-bit 2137B diode t25 4 F8 military standard mpc107 MPC107 PC107A PC7400 transistor pc107 PDF

    diode t25 4 B9

    Abstract: diode t25 4 L5 g24 motorola module datasheet la 7680 T25 4 h5 AD14 MPC107 PC107A PC7400
    Text: Features • Processor Bus Frequency up to 100 MHz • 64-bit or 32 bits Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible


    Original     		64-bit 32-bit diode t25 4 B9 diode t25 4 L5 g24 motorola module datasheet la 7680 T25 4 h5 AD14 MPC107 PC107A PC7400 PDF

    PC7400

    Abstract: No abstract text available
    Text: Features H Processor bus frequency up to 100 MHz. H 64-bit or 32 bits data bus and 32-bit address bus. H Provides support for either asynchronous SRAM, burst SRAM, or pipelined burst SRAM. H Compliant with PCI specification, revision 2.1. H PCI interface operates up to 66 MHz/5.0 Volt compatible.


    Original     		64-bit 32-bit PC107A PC7400 PDF

    Untitled

    Abstract: No abstract text available
    Text: Features H Processor bus frequency up to 100 MHz. H 64-bit or 32 bits data bus and 32-bit address bus. H Provides support for either asynchronous SRAM, burst SRAM, or pipelined burst SRAM. H Compliant with PCI specification, revision 2.1. H PCI interface operates up to 66 MHz/5.0 Volt compatible.


    Original     		64-bit 32-bit PC107A PDF

    i960 sb

    Abstract: Intel i960 features intel i960 RISC intel microprocessor 32 bit pin diagram i960 mc errata Intel i960 architecture intel i960 80960SB embedded microprocessors
    Text: 272234-004.qxd 12/26/00 9:59 AM Page 1 product brief i960 SA/SB 32-Bit Embedded Microprocessors with a 16-Bit Burst Data Bus Product Highlights developer.intel.com • High-Performance 32-bit Embedded Architecture ■ High-Speed 16-bit Burst Data Bus ■


    Original     		32-Bit 16-Bit 512-byte 80lead 84-lead USA/1099/IL1973D i960 sb Intel i960 features intel i960 RISC intel microprocessor 32 bit pin diagram i960 mc errata Intel i960 architecture intel i960 80960SB embedded microprocessors PDF

    SRAM 256K

    Abstract: No abstract text available
    Text: 128K x 64/256K x 72 Synchronous Pipelined Burst SRAM 256K x 72 Burst ZBT SRAM Module Family Features ◆ Description Pin compatible module family for pipelined burst SRAM and pipelined burst zero bus turnaround ZBT™ SRAM Low profile 160-lead AMP Free Height Surface Mount Boardto-Board Connector family (5mm-8mm plug options)


    Original     		64/256K IDT7MBV4150 IDT7MBV4151 IDT7MBV4152 160-lead 66MHz, IDT7MBV4150/51/52 7MBV4150 7MBV4151 7MBV4152 SRAM 256K PDF

    AN-630

    Abstract: C1995 NS32532 NS32GX AN630 NS32GX32
    Text: National Semiconductor Application Note 630 Zeev Bikowsky Aharon Ostrer July 1989 INTRODUCTION The NS32GX32 burst mode is a mechanism for increasing the bus transfer rate Implementing the burst mode enables the CPU to read 4 double words in 5 cycles During nonburst


    Original     		NS32GX32 32-bit 20-3A AN-630 C1995 NS32532 NS32GX AN630 PDF

    AM79C900

    Abstract: 32 bit risc processor using vhdl AM79C940 R3051 R3052 R3081
    Text: Simulation Tools / Models Papillon Research Corp. VHDL MODELS for the R3051 family of RISC Processors Standard Features ❏ Full bus mastership/arbitration ❏ Single reads/writes ❏ Burst reads ❏ Page detect for burst pin ❏ File defined timing ❏ Complete timing checks


    Original     		R3051TM R3041, R3051, R3052, R3071 R3081 R3051 AM79C900 32 bit risc processor using vhdl AM79C940 R3051 R3052 R3081 PDF

    intel i960 RISC

    Abstract: ZN1331 ZIETNET ZEITNET
    Text: ATM ZIETNET, INC. ZATM EISA Bus ATM Adapter High-Performance • Built-In DMA Bus Mastering Capabilities Reduce CPU Overhead ■ 32-Bit Bus Interface and Burst Mode Capabilities Allow Maximum Transfer Rates For Greater Speed and Efficiency ■ 16 Traffic Shapers Allow For


    Original     		32-Bit intel i960 RISC ZN1331 ZIETNET ZEITNET PDF

    MCF5206

    Abstract: No abstract text available
    Text: SECTION 6 BUS OPERATION The MCF5206 bus interface supports synchronous data transfers that can be terminated synchronously or asynchronously and burst or burst-inhibited between the MCF5206 and other devices in the system. This section describes the function of the bus, the signals that


    OCR Scan     		MCF5206 PDF

    M68040

    Abstract: MC68EC040 MC68LC040 BB 36 931 937 motorola
    Text: INDEX -A - Bus Cycle, 7-29, 7-35, 9-20 BSDL Description, 6-15 Access Control Unit, 1-2, B-4, B-5 Buffer Selection, 7-69 Access Control Unit Register, B-5; Burst Mode Operations, 4-3, 4-11, 5-9 Field Definitions, B -6-B -7 Burst Bus Cycles, s e e Bus Cycles


    OCR Scan     		M68040 MC68EC040 MC68LC040 BB 36 931 937 motorola PDF

    MOSYS

    Abstract: MC8051M36 MC8051M36L-7R5VI 1.8V SRAM
    Text: ♦ MC8051M36 36-Mbit: 1Mx36 M o Sys * Symmetric Pipelined Burst SRAM • High Performance • 133-200MHz Speed grades • 3-1-1-1 Burst Read • 3-1-1-1 Burst Write • 3-1-1-1-1-1-1-1. pipelined operation lu • Symm etric Pipeline • No bus turnaround latency allowing 100% bus efficiency


    OCR Scan     		MC8051M36 36-Mbit: 1Mx36 133-200MHz MC8051M36 MOSYS MC8051M36L-7R5VI 1.8V SRAM PDF

    A23 1101 01A

    Abstract: No abstract text available
    Text: PRELIMINARY « ¿ F CY82C599 CY PRESS Intelligent PCI Bus Controller Features Supports 4 PCI Masters • Provides an interface between the PCI Local Bus and the CPU bus • PCI Bus Rev. 2.0 compliant Supports burst mode PCI accesses to memory space • Supports Intel 486DX, 486DX2,


    OCR Scan     		CY82C599 486DX, 486DX2, 486SX, 486SL, AM486 Cx486S2 CY82C596 CY82C297 82C599-2-27 A23 1101 01A PDF