BMS 13-65 TYPE 0G Search Results

bms 13-65 type 0G

Abstract: BOEING BMS 13-65 HS5938-1 2-1548-1M27 bms 13-65 KTH-2216
Contextual Info: GSD .03 3 HOLES REVISIONS INO en I co en ER 37068 AR 07/18/96 CN 38710 C DCT 6/23/3 I CN 39587 A DCT 8/2 2 /6 2—1548—1M27 STAMP: 91836 125 -9 5 -7 XX XX (DATE CODE) scale NOTES: 1. FOR USE WITH BOEING BMS 13-65 TYPE 0G 2. FOR CABLING INSTRUCTIONS SEE 3 -5 4 6 -1 .

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2171/ADSP-2172/ADSP-2173 FEATURES 30 ns Instruction Cycle Time 33 MIPS from 16.67 MHz Crystal at 5.0 V 50 ns Instruction Cycle Time (20 MIPS) from 10 MHz Crystal at 3.3 V ADSP-2100 Family Code & Function Compatible with

5-pin BMS

Abstract: 27c256 plcc "vector instructions" saturation T 2109
Contextual Info: ANALOG DEVICES Low Cost DSP Microcomputers ADSP-2104/ADSP-2109 FUNCTIONAL BLOCK DIAGRAM SUM M A RY 16-Bit Fixed-Point D SP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

ADSP-2115

Contextual Info: ANALOG DEVICES AD SP-2100 Family DSP Microcomputers ADSP-21 xx SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

sem 2105 16 pin

Contextual Info: ADSP-2100 Family DSP Microcomputers ADSP-21XX ANALOG DEVICES SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

ADSP-21065L

Abstract: ADSP21065LKS200X KHQD TMS 3727
Contextual Info:  DSP Microcomputer ADSP-21065L Preliminary Technical Information ‡ +  ,QVWUXPHQWDWLRQDQG,QGXVWULDO$SSOLFDWLRQV ‡ 6XSHU+DUYDUG$UFKLWHFWXUH&RPSXWHU 6+$5&  RXU,QGHSHQGHQW%XVHVIRU'XDO'DWD

TMS 3727

Contextual Info: BACK  DSP Microcomputer ADSP-21065L Preliminary Technical Information ‡ +  ,QVWUXPHQWDWLRQDQG,QGXVWULDO$SSOLFDWLRQV ‡ 6XSHU+DUYDUG$UFKLWHFWXUH&RPSXWHU 6+$5&  RXU,QGHSHQGHQW%XVHVIRU'XDO'DWD

ADSP-21MSP50A

Contextual Info: ANALOG DEVICES Mixed-Signal Processors with Host Interface Ports ADSP-21 msp50A/55A/56A FEATURES 77 ns Instruction Cycle Time from 13.00 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM 1K Words of On-Chip Data Memory RAM

MIPS26

Abstract: adsp21msp59 HA20 27C512 DIL
Contextual Info: A N A LO G ► D E V IC E S FEATURES 38 ns Instruction Cycle Tim e 26 MIPS from 13.00 MHz Crystal ADSP-2100 Family Code and Function Com patible w ith N ew Instruction Set Enhanced for Bit Manipulation Instructions, M ultiplication Instructions, Biased Rounding, and Global Interrupt Masking

TSE 4041

Abstract: ADSP-21msp56a PGA300 msp50 ADSP-21msp55A ADSP-21msp50 001C 27C64 80C51 HA20
Contextual Info: ► ANALOG DEVICES Mixed-Signal Processor with Host Interface Port ADSP-21 msp50A/55A/56A FEATURES 77 ns Instruction Cycle Time from 13.00 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM 1K Words of On-Chip Data Memory RAM

Contextual Info: ANALOG ► DEVICES ADSP-2100 Family DSP Microcomputers ADSP-21XX FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

Contextual Info: ANALOG DEVICES Mixed-Signal Processor with Host Interface Port ADSP-21 msp50A/55A/56A FEATURES 77 ns Instruction Cycle Time from 13.00 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM 1K Words of On-Chip Data Memory RAM

sp2111

Abstract: SP-2111 plc analog em 231 ADSP-2115-BP-55 marking YJ AM marking code BM 68A
Contextual Info: ANALOG DEVICES □ ADSP-2100 Family DSP Microcomputers ADSP-21 xx FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

Contextual Info: ANALOG DEVICES □ FEATURES 30 ns Instruction Cycle Time 33 MIPS from 16.67 MHz Crystal at 5.0 V 38 ns Instruction Cycle Time (26 MIPS) from 13 MHz Crystal at S.O V ADSP-2100 Family Code & Function Compatible with New Instruction Set Enhancements for Bit Manipula­

TSE 4041

Abstract: ADSP-21msp50 msp50 21msp50 MHDR1 HA20
Contextual Info: ANALOG DEVICES INC fc.SE » A N A LO G ► DEVICES FEATURES 77 ns Instruction Cycle Time from 13.00 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM 1K Word of On-Chip Data Memory RAM 2K Words of On-Chip Program Memory ROM

TSE 4041

Abstract: IMX17 144 PGA AS C2 DAB Clock Radio service manual
Contextual Info: ANALOG DEVICES Mixed-Signal Processor with Host Interface Port ADSP-21 msp50A/55A/56A FEATURES 77 ns Instruction Cycle Time from 13.00 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM 1K Words of On-Chip Data Memory RAM

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2186 FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Contextual Info: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 ANALOG DEVICES SUMMARY High Performance Signal Processor for Communica­ tions, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,

CSP-01

Abstract: CSP01 ADSP-2100 12DT8
Contextual Info: ANALOG ► DEVICES Concurrent Signal Processor ADSP-21csp01 FEATURES PERFORMANCE 20 ns Instruction Cycle Tim e from 25 MHz Crystal @ 5.0 V 50 MIPS Sustained Performance 24-Bit Address Bus w ith a Unified 16M Address Space 32 Flexible Data Registers Provide Local Variable Storage

Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb® Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In-Circuit Emulation • 2K Bytes Internal RAM • Fully-program mable External Bus Interface (EBI)

Contextual Info: September 1996 ADSP-2185/ADSP-2185L Preliminaiy Data Sheet For current information contact Analog Devices at 617 461-3881 ADSP-2185/ADSP-2185L DSP Microcomputers FEATURES Performance • 30 n s I n s t r u c t i o n C y c le T im e @ 5.0 V o lts , 33 M IP S S u s ta in e d P e r f o r m a n c e

LDR type orp 12

Abstract: J 292 0 B3 lorb AT91M63200 PA-23s
Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb® Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In-Circuit Emulation • 2K Bytes Internal RAM • Fully-program mable External Bus Interface (EBI)

adqr

Abstract: LBIT 204 AT91M63200 "32-Bit Microcontroller"
Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb® Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In-Circuit Emulation • 2K Bytes Internal RAM • Fully-program mable External Bus Interface (EBI)

Contextual Info: □ ANALOG DEVICES DSP Microcomputer ADSP-2181 FEATURES PERFORMANCE 30 ns Instruction Cycle Time from 16.67 MHz Crystal @ 5.0 Volts 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby