BL753 Search Results

Contextual Info: SN74ALS874B, SN74ALS876A, SN74AS874, SN74AS876 SN54ALS874B, SN54AS874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS D2661. APRIL 1982 - REVISED MAY 198$ 3-State Buffer-Type Outputs Drive Bus-Lines Directly S N 5 4A LS 8 74 B , S N 5 4 A S 8 7 4 . . . J T PACKAGE

HCT244

Abstract: SN54HCT244 SN74HCT244 01G50
Contextual Info: SN54HCT244, SN74HCT244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS _ S C L S 1 7 5 A -M A R C H 1 984 - REVISED JAN U A R Y 1996 Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers High-Current Outputs Drive up to 15 LSTTL

LVTH16244A

Abstract: SN54LVTH16244A SN74LVTH16244A
Contextual Info: SN54LVTH16244A, SN74LVTH16244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS S C BS142H - M A Y 1 9 9 2 - R E V IS E D D E C E M B E R 1996 SN54LVTH16244A . . . WD PACKAGE SN74LVTH16244A . . . DGG OR DL PACKAGE TOP VIEW State-of-the-Art Advanced BiCMOS

P34S8

Abstract: 74ACT11648
Contextual Info: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS115 - P34S8, MARCH 1990 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Independent Registers A and B Buses _ J — o — u G [ 1 28 ] C A B Multiplexed Real-Time and Stored Data

Contextual Info: CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS SCAS335 - DECEMBER 1992 - REVISED MARCH 1994 * Low Output Skew for Clock-Distribution and Clock-Generation Applications * TTL-Compatible Inputs and CMOS-Compatible Outputs * Distributes One Clock Input to Six Clock

SN74ACT7811

Abstract: SN74ACT7881 SN74ACT7882 SN74ACT7884 SN74ACT
Contextual Info: SN74ACT7882 2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS445 - JUNE 1994 * Member of the Texas Instruments Widebus Family * Input-Ready, Output-Ready, and Half-Full Flags * Independent Asynchronous Inputs and Outputs * Cascadable in Word Width and/or Word

Contextual Info: SN54AS821A, SN74AS821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS S D A S 2 3 0 A - D E C E M B E R 198 3 - R E V IS E D A U G U S T 1 9 9 5 Functionally Equivalent to AMD’s AM29821 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With

SN74ALVCH16240

Contextual Info: SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SC ES045- JULY 1995 DGQ OR DL PACKAGE TOP VIEW Member of the Texas Instruments Wldebus Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds

SN54LVT18502

Abstract: LVT18502 LVT182502 SN74LVT182502 SN74LVT18502 GSM Transceiver 1994
Contextual Info: SN54LVT18502, SN54LVT182502, SN74LVT18502, SN74LVT182502 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS Members of the Texas Instruments SCOPE Family of Testability Products Members of the Texas Instruments Widebus ™ Family Compatible With the IEEE Standard

SN74ALS161

Abstract: 30715 SN54ALS161B SN54ALS163B SN54AS161 SN54AS163 SN74ALS161B SN74ALS163B SN74AS161 SN74AS163
Contextual Info: SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SEM54ALS161B, SN54ALS163B, SN54AS161, SN54AS163 SYNCHRONOUS 4-BIT BINARY COUNTERS _ Internal Look-Ahead for Fast Counting D 2 6 6 1 , A P R IL 1 9 82 - R E V IS E D M A Y 1986 S N 5 4A LS ', S N 5 4A S ' . . . J PACKAGE

Contextual Info: 54ACT11004, 74ACT11004 HEX INVERTERS SC A S 215 - D2957, JANUARY 1988 - RE V IS E D APRIL 1993 • * Inputs Are TTL-Voltage Compatible ■ I * Flow-Through Architecture Optimizes PCB Layout V I * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise

SN74LVC544

Contextual Info: SN74LVC544 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS S C A S 3 4 6 - MARCH 1994 DB, DW, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25°C

Contextual Info: 74ACT11194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER D3391, NOVEMBER 1989 - REVISED APRIL 1993 • I I DW OR N PACKAGE TOP VIEW * Inputs Are TTL-Voltage Compatible * Parallel-to-Serlal, Serlal-to-Parallel Conversions I * Left or Right Shifts I * Parallel Synchronous Loading