B35B Search Results

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Abstract: tea 2030 T5ooo Nippon capacitors
Contextual Info: MOTOROLA Order Number: MPC850ABEC/D Rev. 0, 9/1999 Semiconductor Products Sector Advance Information MPC850 Rev. A/B Hardware Specifications This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC timing specifications for revision A and B o f the MPC850.

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024x36x2 Integrated Device Technology, Inc. PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • M aster R eset clears d ata and configures FIFO, Partial R eset clears data but retains configuration settings

Contextual Info: | CMOS Bus-Matching SyncFlFO 256 x 36, 512 x 36,1,024 x 36 dt PRELIMINARY ¡DT723633 IDT723643 Integrated D ev ic e Techno logy, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping IDT723613 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity FIFO buffering data from Port A

cn/A/U 237 BG

Contextual Info: SIEMENS High-Performance 8-Bit CMOS Single-Chip Microcontroller SAB 80C517/80C537 Advanced Information SAB 80C517 SAB 80C537 Microcontroller with factory mask-programmable ROM Microcontroller for external ROM • Fast 32-bit division, 16-bit 2 multiplication,

Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

322120S-70

Abstract: HYB514400
Contextual Info: SIEMENS 2 M X 32-Bit Dynamic RAM Module HYM 322120S-60/-70/-80 Advanced Information • 2 097 152 words by 32-Bit organization alternative 4 194 304 words by 16-Bit • Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time

Contextual Info: 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • Passive parity checking on each Port • Parity Generation can be selected for each Port • Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)

Contextual Info: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: Integrated Device TechnoJogy, lie. PRELIMINARY IDT723624 IDT723634 IDT723644 CMOS Sync BiFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

723674

Abstract: IDT723654 IDT723664 IDT723674
Contextual Info: CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2 FEATURES: PRELIMINARY IDT723654 IDT723664 IDT723674 ♦ Port B bus sizing of 36 bits long word , 18 bits (word) and 9 bits (byte) ♦ Big- or Little-Endian format for word and byte bus sizes

MPC850

Abstract: MPC850DE MPC850SAR MPC860 XPC850ZT50B
Contextual Info: Advance Information MPC850EC/D Rev. 0.1, 11/2001 MPC850 Rev. A/B Communications Controller Hardware Specifications This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC timing specifications for revision A and B of the MPC850.

MPC860EC

Abstract: MC68360 MPC855T MPC860 MPC860DE MPC860DP MPC860DT MPC860EN MPC860P MPC860SR
Contextual Info: Freescale Semiconductor, Inc. Advance Information MPC860EC Rev. 6.3 9/2003 Freescale Semiconductor, Inc. MPC860 Family Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC860 family.

IDT723623

Abstract: IDT723633 IDT723643 B35b
Contextual Info: CMOS Bus-Matching SyncFIFO 256 x 36, 512 x 36, 1,024 x 36 PRELIMINARY IDT723623 IDT723633 IDT723643 Integrated Device Technology, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

Contextual Info: CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36 4,096 x 36 8,192 x 36 • • • FEATURES • • • • • • • Memory storage capacity: IDT723653 – 2,048 x 36 IDT723663 – 4,096 x 36 IDT723673 – 8,192 x 36 Clock frequencies up to 83 MHz 8 ns access time

IC51-1324-828

Abstract: IDT723613 IDT72V3613
Contextual Info: IDT72V3613 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 FEATURES: ♦ ♦ ♦ Passive parity checking on each Port Parity Generation can be selected for each Port Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 2 5 6 x 3 6 x 2, 512 x 3 6 x 2, 1,024 x 36 x 2_ FEATURES: • Memory storage capacity: IDT72V3624-256 x 36 x 2 IDT72V3634-512 x 36 x 2 IDT72V3644-1,024x36x2 • Clock frequencies up to 83 MHz 8ns access time

Contextual Info: CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36 FEATURES: • • • • • • • • • Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 Clocked FIFO buffering data from Port A to Port B Clock frequencies up to 83 MHz 8 ns access time

Contextual Info: IDT72V3613 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • • FEATURES: • • • • • • • • • • • • • 64 x 36 storage capacity FIFO buffering data from Port A to Port B Supports clock frequencies up to 83MHz

723674

Contextual Info: 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 • • • FEATURES • • • • • • • Memory storage capacity: IDT72V3654 – 2,048 x 36 x 2 IDT72V3664 – 4,096 x 36 x 2 IDT72V3674 – 8,192 x 36 x 2 Clock frequencies up to 100 MHz 6.5ns access time

IDT723624

Abstract: IDT723634 IDT723644
Contextual Info: CMOS SyncBiFIFO with Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Integrated Device Technology, Inc. IDT723624 IDT723634 IDT723644 • Port B bus sizing of 36-bits long word , 18-bits (word) and 9-bits (byte) • Big- or Little-Endian format for word and byte bus sizes

BV 3145

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36 FE ATURES: • Free-running CLKA and CLKB may be asynchronous or coincident perm its sim ultaneous reading and w riting ot data on a single clock edge • 64 x 36 storage capacity FIFO buttering data trom Port A

cmc tpm 16

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping Integrated Device Technology, Inc. IDT723613 6 4 x 3 6 FEATURES: • Free-running C LKA and CLKB may be asynchronous or coincident perm its sim ultaneous reading and w riting of data on a single clock edge

U/25/20/TN26/15/850/ic tea 810 datasheet

Contextual Info: Freescale Semiconductor Document Number: MPC850EC Rev. 2, 07/2005 Technical Data MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC