ASIC CADENCE TOOL Search Results

ASIC CADENCE TOOL Result Highlights (5)

Part	Manufacturer	Description
LBUA5QJ2AB-828EVB	Murata Manufacturing Co Ltd	QORVO UWB MODULE EVALUATION KIT
MYC0409-NA-EVM	Murata Manufacturing Co Ltd	72W, Charge Pump Module, non-isolated DC/DC Converter, Evaluation board
37-1409	Coilcraft Inc	Tuning tool
37-2182	Coilcraft Inc	Tuning tool
AXL-A	Coilcraft Inc	Test fixture for axial lead components

ASIC CADENCE TOOL Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: DIGITAL SEMICUSTOM CIRCUITS SEMICUSTOM DESIGN TOOLS SGS-THOMSON ASIC DESIGN KITS Type Description Cadence ASIC Design Kit ADK SUN based. Includes support for Verilog, Veritime, Verifault. Delay calculator with RC-backannotation. Module Generators. EWS interface.	Original		PDF
80C51 Abstract: TMS320C50 scl* by national TMS320C50 architecture Text: N Customizable Solutions – ASIC N Customizable Solutions – ASIC Table of Contents National Semiconductor offers customizable “systems-on-a-chip” solutions to all process flows and extensive packaging options. A unique competency-based alliance with Cadence Design Systems and Aspec Technology	Original		PDF
Atmel 540 Abstract: Pin-for-Pin Compatible Text: Atmel Design Tools Netlist Checker Test Vector Checker Delay Calculator/ Back Annotation Computer System Version Simulator and Schematic Capture Cadence/Composer 1.3 2.0 4.2 Veritime/ Verilog-XL/ Composer v3 tvc Yes Sun 4, HP Viewlogic 5.1-PC 5.3-Sun ViewSIM, ViewDRAW	Original	386/486/PentiumTM Atmel 540 Pin-for-Pin Compatible	PDF
ternary content addressable memory VHDL Abstract: ARM1020E SMART ASIC bga ARM dual port SRAM compiler Samsung ASIC 0.13um standard cell library Standard Cell 0.13um System-On-Chip ASIC DSPG samsung lcd JTAG "content addressable memory" precharge Text: V S MSUNG STDL150 ELECTRONICS STDL150 Standard Cell 0.13um System-On-Chip ASIC March 2003, V2.0 Features Analog cores - Ldrawn = 0.13um 1.5/2.5/3.3V Device 1.5/2.5/3.3V - Up to 45.8 million gates Interface - Power dissipation: 13nW/MHz@1.5V, 2SL, ND2 5.0V	Original	STDL150 STDL150 13nW/MHz ARM920T/ARM940T, ternary content addressable memory VHDL ARM1020E SMART ASIC bga ARM dual port SRAM compiler Samsung ASIC 0.13um standard cell library Standard Cell 0.13um System-On-Chip ASIC DSPG samsung lcd JTAG "content addressable memory" precharge	PDF
ARM9TDMI Abstract: ARM1020E samsung hdd Samsung S ARM teaklite DSPG SMART ASIC bga ARM920t datasheet Avant Electronics USB samsung Text: V S MSUNG STDH150 ELECTRONICS STDH150 Standard Cell 0.13um System-On-Chip ASIC Dec 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 34.3 million gates - Power dissipation:9nW/MHz@1.2V, 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STDH150 STDH150 ARM920T/ARM940T, ARM9TDMI ARM1020E samsung hdd Samsung S ARM teaklite DSPG SMART ASIC bga ARM920t datasheet Avant Electronics USB samsung	PDF
ARM dual port SRAM compiler Abstract: DSPG teaklite ARM9TDMI ARM1020E samsung hdd UART 16C450 Standard Cell 0.13um System-On-Chip ASIC ARM920T ARM926EJ Text: V S MSUNG STD150 ELECTRONICS STD150 Standard Cell 0.13um System-On-Chip ASIC Oct 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 46 million gates - Power dissipation:9nW/MHz@1.2V, 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STD150 STD150 ARM920T/ARM940T, ARM dual port SRAM compiler DSPG teaklite ARM9TDMI ARM1020E samsung hdd UART 16C450 Standard Cell 0.13um System-On-Chip ASIC ARM920T ARM926EJ	PDF
TGC2000 Abstract: memory compiler docs Text: ASIC TGC2000 Family SGYV047A November 1998 Highlights: Many of today’s military ASIC designs require a mature, cost-effective 5-volt technology. Optimized for high performance at 5-volt operation, TI’s 0.55 µm CMOS ASIC family,	Original	TGC2000 SGYV047A TGC2000, MIL-PRF-38535 5962-96B01 5962-97B01 memory compiler docs	PDF
ARM dual port SRAM compiler Abstract: rm2510 synopsys dc ultra DSPG 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 Text: V S MSUNG STD130 ELECTRONICS STD130 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device	Original	STD130 STD130 24nW/MHz ARM920T/ARM940T, ARM dual port SRAM compiler rm2510 synopsys dc ultra DSPG 16C450 16C550 ARM920T ARM940T IEEE1284 STD110	PDF
ARM1020E Abstract: samsung hdd Samsung Soc processor 4468 8 pin ARM920t datasheet ARM9TDMI DSPG ARM SRAM compiler UART 16C450 ARM940T Text: V S MSUNG STD150 ELECTRONICS STD150 Standard Cell 0.13um System-On-Chip ASIC Oct 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 46 million gates - Power dissipation:9nW/MHz@1.2V, 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STD150 STD150 ARM920T/ARM940T, ARM1020E samsung hdd Samsung Soc processor 4468 8 pin ARM920t datasheet ARM9TDMI DSPG ARM SRAM compiler UART 16C450 ARM940T	PDF
DSPG Abstract: Samsung Soc processor STD110 ASIC 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 piler Text: V S MSUNG STD131 ELECTRONICS STD131 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device	Original	STD131 STD131 24nW/MHz ARM920T/ARM940T, DSPG Samsung Soc processor STD110 ASIC 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 piler	PDF
TGC4000 Abstract: memory compiler Text: ASIC TGC4000 Family SGYV048A November 1998 Highlights: As the complexity of designs continue to increase, it is important to choose an ASIC technology that will meet all the design goals, not just the gate count. TGC4000 was	Original	TGC4000 SGYV048A MIL-PRF-38535 5962-96B04 memory compiler	PDF
memory compiler Abstract: GS20 Text: Fact Sheet M i l i t a r y S e m i c o n d u c t o r P r o d u c t s ASIC GS20 SGYV062B October 1999 Highlights: Whether you are pushing the envelope of today's technology, or you need a design solution for your high-volume application, TI's GS20 ASIC family is for you. GS20 is	Original	SGYV062B memory compiler GS20	PDF
atmel13 Abstract: 0.18-um CMOS technology characteristics DIGITAL IC TESTER report for project ATMEL 644 IO33 IC Ensemble ATC18RHA IBIS model Genibis Atmel IO33 ATC18RHA atmel 336 Text: Features • Comprehensive Library of Standard Logic and I/O Cells • ATC18RHA Core and IO18 pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main • • • • • • • • • • • • Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V Environments	Original	ATC18RHA 655Mbps) 4261B atmel13 0.18-um CMOS technology characteristics DIGITAL IC TESTER report for project ATMEL 644 IO33 IC Ensemble IBIS model Genibis Atmel IO33 ATC18RHA atmel 336	PDF
XAPP140 Abstract: ASIC CADENCE TOOL Text: Application Note: FPGAs R Physical Synthesis Author: Hamid Agah XAPP140 v1.0 February 26, 2001 Why is Physical Synthesis Necessary? In the domain of deep submicron (DSM) and nanometer ASIC technologies (180 nm and below), the traditional separation between logical (synthesis) and physical (place and route)	Original	XAPP140 XAPP140 ASIC CADENCE TOOL	PDF

Atmel 544 Abstract: atmel 504 atmel 404 MQFPT352 MLGA625 725m 5962-06B02 atmel h 404 MH1242E 404D Text: Features • • • • • • • • • • • • • • • • • Comprehensive Library of Standard Logic and I/O Cells Up to 6.5 usable Mgates equivalent NAND2 Operating voltage 1.8V for core and 3.3V or 2.5V for I/O’s Memory Cells Compiled or synthesized to the Requirements of the Design	Original	655Mbps) 4261G Atmel 544 atmel 504 atmel 404 MQFPT352 MLGA625 725m 5962-06B02 atmel h 404 MH1242E 404D	PDF
DIGITAL IC TESTER report for project Abstract: atmel 504 IO33 ATC18RHA 4261C virage IO33 Text: Features • Comprehensive Library of Standard Logic and I/O Cells • ATC18RHA Core and IO18 pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main • • • • • • • • • • • • • • Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V Environments	Original	ATC18RHA 655Mbps) 4261C DIGITAL IC TESTER report for project atmel 504 IO33 ATC18RHA virage IO33	PDF
memory compiler Abstract: No abstract text available Text: Fact Sheet M i l i t a r y S e m i c o n d u c t o r P r o d u c t s ASIC GS30 SGYV067A February 2000 Highlights: GS30 uses Texas Instruments TImeCell Architecture, which combines the costefficiency of standard cells with the fast time-to-market of gate arrays on the same	Original	SGYV067A memory compiler	PDF
PT6042 Abstract: PT6045 VSC350 PT6005 nd02d2 Text: V L S I TECHNOLOGY INC 47 E D =1350347 0 0 0 0 0 3 0 VTI V L S I Technology , in c VSC350 SERIES 1-MICRON HIGH-PERFORMANCE STANDARD CELL LIBRARY FEATURES • Fast design turn-around time with COMPASS Design Automation’s advanced design tools and methodology	OCR Scan	VSC350 85-micron T-42-41 PT6042 PT6045 PT6005 nd02d2	PDF
DIGITAL IC TESTER report for project Abstract: ATMEL 644 IO33 4261F ATC18RHA Genesys Logic MQFP-F196 5962-06B02 atmel 216 4261b Text: Features • • • • • • • • • • • • • • • • Comprehensive Library of Standard Logic and I/O Cells ATC18RHA Core pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V and 2.5 +/- 0.25V Environments	Original	ATC18RHA 655Mbps) 4261F DIGITAL IC TESTER report for project ATMEL 644 IO33 Genesys Logic MQFP-F196 5962-06B02 atmel 216 4261b	PDF
DIGITAL IC TESTER report for project Abstract: MCGA349 PL33RXZ atmel 504 ATMEL 644 ATC18RHA 5962-06B02 MQFP-T352 IO33 mcga Text: Features • • • • • • • • • • • • • • • • Comprehensive Library of Standard Logic and I/O Cells ATC18RHA Core pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V and 2.5 +/- 0.25V Environments	Original	ATC18RHA 655Mbps) 4261E DIGITAL IC TESTER report for project MCGA349 PL33RXZ atmel 504 ATMEL 644 5962-06B02 MQFP-T352 IO33 mcga	PDF
U2550 Abstract: u560100 ZMD U2510 U560244 Bosch Common Rail Sensor U2400 6v to 7.5v dc power supply circuit project U560048 U2100 u5601 Text: Mixed-signal ASICs - brilliant ideas developed through dialogue with our customers Mixed-signal ICs from ZMD - system solutions that meet exacting requirements, containing a high proportion of analog circuit components. These ICs typically provide cost-effective on-chip calibration,	Original		PDF
verilog hdl code for triple modular redundancy Abstract: Cyclic Redundancy Check simulation Single Event Latchup FPGA 30-80LET ACT 1 FPGA actel Text: Real Time Verification/Programming Finishing the Job A c t e l ASICmaster is an automatic place and route tool that runs on SunOS , Solaris®, and HPUX®, as well as on Windows® NT™ . ASICmaster accepts standard ASIC formatted netlists and performs timing-driven place and route. Incremental place and route is supported for	Original	200MHz verilog hdl code for triple modular redundancy Cyclic Redundancy Check simulation Single Event Latchup FPGA 30-80LET ACT 1 FPGA actel	PDF
ATMEL 644 Abstract: atmel 340 verilog code for half subtractor Gate level simulation atmel 644 datasheet 0.18-um CMOS standard cell library inverter Verilog code subtractor AMBIT inverter ambit rev 4 IBIS model Genibis Atmel Text: Features • Comprehensive Library of Standard Logic and I/O Cells • ATC18 Core and I/O Cells Designed to Operate with VDD = 1.8V ± 0.15V as Main Target Operating Conditions • IO33 Pad Libraries Provide Interfaces to 3V Environments • Memory Cells Compiled to the Precise Requirements of the Design	Original	ATC18 ATMEL 644 atmel 340 verilog code for half subtractor Gate level simulation atmel 644 datasheet 0.18-um CMOS standard cell library inverter Verilog code subtractor AMBIT inverter ambit rev 4 IBIS model Genibis Atmel	PDF
verilog advantages disadvantages Abstract: verilog hdl code for multiplexer 4 to 1 vhdl code for 7400 vhdl code for ROM multiplier verilog disadvantages RTL code for ethernet Gate level simulation without timing digital clock verilog code vhdl code for rs232 altera structural vhdl code for multiplexers Text: Design Tools for 100,000 Gate Programmable Logic Devices March 1996, ver. 1 Introduction Product Information Bulletin 22 The capacity of programmable logic devices PLDs has risen dramatically to meet the need for increasing design complexity. Now that	Original	000-gate verilog advantages disadvantages verilog hdl code for multiplexer 4 to 1 vhdl code for 7400 vhdl code for ROM multiplier verilog disadvantages RTL code for ethernet Gate level simulation without timing digital clock verilog code vhdl code for rs232 altera structural vhdl code for multiplexers	PDF

ASIC CADENCE TOOL Search Results

ASIC CADENCE TOOL Result Highlights (5)

ASIC CADENCE TOOL Datasheets Context Search

Untitled

80C51

Atmel 540

ternary content addressable memory VHDL

ARM9TDMI

ARM dual port SRAM compiler

TGC2000

ARM dual port SRAM compiler

ARM1020E

DSPG

TGC4000

memory compiler

atmel13

XAPP140

Atmel 544

DIGITAL IC TESTER report for project

memory compiler

PT6042

DIGITAL IC TESTER report for project

DIGITAL IC TESTER report for project

U2550

verilog hdl code for triple modular redundancy

ATMEL 644

verilog advantages disadvantages