AS7C3512K18P Search Results

AS7C3512K18P Datasheets (5)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
AS7C3512K18P-4BC		Alliance Semiconductor	3.3V 512K x 18 pipeline burst synchronous SRAM		Original	PDF
AS7C3512K18P-4BQC		Alliance Semiconductor	3.3V 512K x 18 pipeline burst synchronous SRAM		Original	PDF
AS7C3512K18P-4TQC		Alliance Semiconductor	3.3V 512K x 18 pipeline burst synchronous SRAM		Original	PDF
AS7C3512K18P-5BC		Alliance Semiconductor	3.3V 512K x 18 pipeline burst synchronous SRAM		Original	PDF
AS7C3512K18P-5TQC		Alliance Semiconductor	3.3V 512K x 18 pipeline burst synchronous SRAM		Original	PDF

AS7C3512K18P Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
A301D Abstract: A211D 4bc 82 Text: $GYDQFHLQIRUPDWLRQ $6&.3 $6&.3 9.ðSLSHOLQHEXUVWV\QFKURQRXV65$0 HDWXUHV • Multiple packaging options - Economical 100-pin TQFP package - Chip-scale fBGA package for smallest footprint • Byte write enables • Clock enable for operation hold	Original	SLSHOLQHEXUVWV\QFKURQRXV65 100-pin AS7C3512K16P-5TQC AS7C3512K18P-3 AS7C3512K18P-4TQC AS7C3512K18P-5TQC AS7C3512K16P-3 AS7C3512K16P-4BC A301D A211D 4bc 82	PDF
Untitled Abstract: No abstract text available Text: $GYDQFHLQIRUPDWLRQ $6&.= $6&.= 9.ðV\QFKURQRXVEXUVW65$0ZLWK=%7 HDWXUHV • ZZ sleep mode for lower power • Byte write enables • Single R/W control pin • Clock enable for operation hold • Multiple chip enables for easy expansion	Original	\QFKURQRXVEXUVW65 AS7C3512K18P) AS7C3512K16Z-3 AS7C3512K16Z-4TQC AS7C3512K16Z-5TQC AS7C3512K18Z-3 AS7C3512K18Z-4TQC AS7C3512K18Z-5TQC AS7C3512K16Z-4BC	PDF
Untitled Abstract: No abstract text available Text: Advance information •■ AS7C3512K16P AS7C3512K18P Il II 3.3V 512K- 16 ‘18 pipeline burst synchronous SRAM Features • • • • • • • • • Organization: 5 2 4 ,2 8 8 w ord s x 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3 . 5 / 3 . 8 / 4 / 5 ns	OCR Scan	AS7C3512K16P AS7C3512K18P 100-pin IPC-SM-782	PDF
siti Abstract: nas77 3512K Text: Features • • • • • • • • • Organization: 5 2 4 ,2 8 8 w ords x 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access'. 3 . 5 / 3 . 8 / 4 / 5 ns Fast UE access time: 3 . 5 / 3 . 5 / 3 . 8 / 4 ns Fully synchronous register-to-register operation	OCR Scan	100-pin 16P-4T 18P-4T 3512K 16P-5T AS7C3512K18P AS7C3512K16P siti nas77	PDF
Untitled Abstract: No abstract text available Text: Advance information •■ I l AS7C3512K16Z AS7C3512K18Z A 3.3V 5 1 2K x 1 6 /1 8 synchronous burst SRAM with ZBT1 Features • • • • • • • • • • • • • • • • • • • Organization: 524,288 words x 16 or 18 bits ZBT architecture for efficient bus operation	OCR Scan	AS7C3512K16Z AS7C3512K18Z 100-pin f3512K16Z-4TQC AS7C3512K16Z-5TQC AS7C3512K18Z-3 AS7C3512K18Z-4TQC AS7C3512K18Z-5TQC AS7C3512K16Z-3 AS7C3512K16Z-4BC	PDF
AIA4M Abstract: VW99 Text: Advance informatio AS7C3512K16Z AS7C3512K18Z •3V 5 1 2 K x l 6 / 1 8 synchronous burst SRAM with ZBT Features • • • • • • • • • • ZZ sleep mode for lower power Byte write enables Single R/ W control pin Gock enable for operation hold	OCR Scan	3V512KX16/18 AS7C3512K16Z AS7C3512K18Z 100-pin AS7C3512K16Z-3 AS7C3512K16Z-4TQC AS7C3512K16Z-5TQC AS7C3512K18Z-3 AS7C3512K18Z-4TQC AS7C3512K18Z-5TQC AIA4M VW99	PDF
L8150 Abstract: No abstract text available Text: Features • • • • • • • • • • • ZZ sleep m ode for lower power • Byte write enables • Single R /W control pin • Clock enable for operation hold • Multiple chip enables for easy expansion •3 .3 V ± 5 % core power supply • 2.5V or 3.3V I/O operation with separate Vppg	OCR Scan	100-pin 3512K 512K18 L8150	PDF