AS7C33256NTD16A Search Results

Contextual Info: January 2001 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features • Organization: 262,144 words x 16 or 18 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

Contextual Info: September 2002 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features 1 NTD is a trademark of Alliance Semiconductor Corporation. • Economical 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion

Contextual Info: Advance information June 2001 AS7C33256NTD16A AS7C33256NTD18A 3.3V 256Kx16/18 SRAM with NTDTM Features • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ

Contextual Info: February 2002 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features 1 NTD is a trademark of Alliance Semiconductor Corporation. • Economical 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion

Contextual Info: Advance information April 2001 AS7C33256NTD16A AS7C33256NTD18A 3.3V 256Kx16/18 SRAM with NTDTM Features • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ

Contextual Info: February 2002 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features • Organization: 262,144 words x 16 or 18 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

Contextual Info: Advance information January 2001 AS7C33256NTD16A AS7C33256NTD18A 3.3V 256Kx16/18 SRAM with NTD T M Features • Organization: 262,144 words × 16 or 18 bits • NTD architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS

AS7C33256NTD18A

Abstract: WJ-A22
Contextual Info: December 2002 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features 1 NTD is a trademark of Alliance Semiconductor Corporation. • Economical 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion

AS7C33256NTD18A

Contextual Info: March 2002 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features 1 NTD is a trademark of Alliance Semiconductor Corporation. • Economical 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion

Contextual Info: January 2001 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features • Organization: 262,144 words x 16 or 18 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

dsp processor Architecture of TMS320C6X

Abstract: AS7C33256PFD16A AS7C33256PFD18A AS7C33256PFS16A AS7C33256PFS18A TMS320C6X
Contextual Info: March 2001 AS7C33256PFD16A AS7C33256PFD18A 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns

Contextual Info: AS7C33256PFS16A AS7C33256PFS18A December 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power-down mode

Contextual Info: AS7C33256PFS16A AS7C33256PFS18A April 2001 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

Contextual Info: AS7C33256PFS16A AS7C33256PFS18A September 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power-down mode

Contextual Info: November 2000 Advance Information AS7C33256PFS16A AS7C33256PFS18A 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: December 2000 Advance Information AS7C33256PFS16A AS7C33256PFS18A 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: April 2001 AS7C33256PFD16A AS7C33256PFD18A 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

AS7C33256PFD16A

Abstract: AS7C33256PFD18A AS7C33256PFS16A AS7C33256PFS16A-166TQC AS7C33256PFS16A-166TQI AS7C33256PFS18A TMS320C6X
Contextual Info: AS7C33256PFS16A AS7C33256PFS18A March 2001 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns

Contextual Info: AS7C33256PFD16A AS7C33256PFD18A January 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Byte write enables • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power down mode

Contextual Info: January 2001 Advance Information AS7C33256PFD16A AS7C33256PFD18A 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: AS7C33256PFS16A AS7C33256PFS18A January 2001 Preliminary Information 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

AS7C33256

Contextual Info: AS7C33256PFD16A AS7C33256PFD18A January 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Byte write enables • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power down mode

AS7C33256PFD16A

Abstract: AS7C33256PFD18A AS7C33256PFS16A AS7C33256PFS18A TMS320C6X
Contextual Info: AS7C33256PFS16A AS7C33256PFS18A January 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

Contextual Info: AS7C33256PFD16A AS7C33256PFD18A September 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/4.0/5.0 ns • Fast OE access time: 3.5/4.0/5.0 ns