AS7C332 Search Results

dsp processor Architecture of TMS320C6X

Abstract: AS7C33256PFD16A AS7C33256PFD18A AS7C33256PFS16A AS7C33256PFS18A TMS320C6X
Contextual Info: March 2001 AS7C33256PFD16A AS7C33256PFD18A 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns

AS7C33256PFS18B-166TQC

Contextual Info: AS7C33256PFS16B AS7C33256PFS18B October 2003 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features •Byte write enables •Multiple chip enables for easy expansion •3.3V core power supply •2.5V or 3.3V I/O operation with separate VDDQ •30 mW typical standby power in power down mode

Contextual Info: AS7C33256PFS16A AS7C33256PFS18A December 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power-down mode

Contextual Info: February 2002 AS7C33256NTD32A AS7C33256NTD36A Š 9 .î 65$0 ZLWK 17'TM 1 Features • Organization: 262,144 words x 32 or 36 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.5/3.8/4/5 ns

Contextual Info: AS7C33256PFS16A AS7C33256PFS18A April 2001 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

Contextual Info: AS7C33256PFS16A AS7C33256PFS18A September 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power-down mode

Contextual Info: AS7C33256PFD16A AS7C33256PFD18A December 2002 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/4.0/5.0 ns • Fast OE access time: 3.5/4.0/5.0 ns

Contextual Info: January 2001 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features • Organization: 262,144 words x 16 or 18 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

10PACKAGE

Contextual Info: September 2001 Preliminary Information AS7C33256PFD32A AS7C33256PFD36A 3.3V 256K x 32/36 pipeline burst synchronous SRAM Features • Organization: 262,144 words x 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: November 2000 Advance Information AS7C33256PFS16A AS7C33256PFS18A 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: AS7C33256PFD18B May 2004 3.3V 256K x 18 pipeline burst synchronous SRAM Features • • • • • • • • • • • • • • • • Organization: 262,144 words × 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/4.0 ns

Contextual Info: December 2004 AS7C33256NTD18B 3.3V 256Kx18 Pipelined SRAM with NTDTM Features • Organization: 262,144 words × 18 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns

Contextual Info: December 2000 Advance Information AS7C33256PFS16A AS7C33256PFS18A 3.3V 256K x 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: September 2002 AS7C33256NTD16A AS7C33256NTD18A 9 .î 65$0 ZLWK 17'TM Features 1 NTD is a trademark of Alliance Semiconductor Corporation. • Economical 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion

Contextual Info: April 2004 AS7C332MPFD18A 3.3V 2M x 18 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • • Organization: 2,097,152 words × 18 bits Fast clock speeds to 200 MHz in LVTTL/LVCMOS Fast clock to data access: 3.1/3.4/3.8 ns

Contextual Info: AS7C33256NTD32A AS7C33256NTD36A May 2003 Š 9 .î 65$0 ZLWK 17'TM Features • Organization: 262,144 words x 32 or 36 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4/5 ns

Contextual Info: Advance information April 2001 AS7C33256NTD32A AS7C33256NTD36A 3.3V 256Kx32/36 SRAM with NTDTM Features • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3 core power supply • 2.5V or 3.3V I/O operation with separate VDDQ

AS7C33128PFD32B

Abstract: AS7C33128PFS32B AS7C33128PFS36B AS7C33256NTF18B AS7C33256PFD18B AS7C33256PFS18B AS7C33256
Contextual Info: April 2005 AS7C33256NTF18B 3.3V 256K x 18 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 262,144 words x 18 bits NTD architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns

AS7C33128PFD32B

Abstract: AS7C33128PFS32B AS7C33128PFS36B AS7C33256FT18B AS7C33256PFD18B AS7C33256PFS18B AS7C33256
Contextual Info: AS7C33256FT18B December 2004 3.3V 256K x 18 Flow Through Synchronous SRAM Features • • • • • • • • • • • • • Organization: 262,144 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns

AS7C331MPFD32A

Abstract: AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A
Contextual Info: December 2004 AS7C332MFT18A 3.3V 2M x 18 Flow-through synchronous SRAM Features • • • • • • • Organization: 2,097152 words × 18 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation

Contextual Info: H ig h P e rfo rm a n ce •■ 32K X 32 ü AS7C33232 A S7C 33232F CMOS SRAM 3 2 K x j ¿ S y n c h ro n o u s burst SRAM Features • Organization: 3 2 ,7 6 8 w o rd s x 32 bits • A synchronou s ou tp u t enable control • Fully syn ch ron ou s p ip e lin ed op eration

AS7C33256NTD32A

Abstract: AS7C33256NTD36A AS7C33256PFD32A AS7C33256PFD36A AS7C33256PFS32A AS7C33256PFS36A
Contextual Info: April 2002 Preliminary AS7C33256PFD32A AS7C33256PFD36A 3.3V 256K x 32/36 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

AS7C33232-15QC

Abstract: datasheet CI 556 ats 2300 intel 8282 AS7C33232-15TQC nt 407 f AS7C33232 MO-108 NT 407 F transistor
Contextual Info: High Performance 32Kx32 CMOS SRAM AS7C33232 AS7C33232F 32K×32 Synchronous burst SRAM Features • Organization: 32,768 words × 32 bits • Fully synchronous pipelined operation • Flow-through option F version • Fast clocking speed: 100/75/66/60 MHz

3232F-7

Abstract: PQFP dimension intel MI-003 pqfp 14x20 100pin
Contextual Info: H igh Perform ance 32KX32 CM O S SRAM AS7C33232F 3 2 K X 3 2 Synchronous burst SRA M Preliminary information Features • • • • • • • • Organization: 32,768 words x 32 bits Fully synchronous pipelined operation Flow-through or pipelined Fast clocking speed: 1 0 0 /7 5 /6 6 MHz