AND8072 Search Results

AND8072 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
AND8072		On Semiconductor	Application Note: Thermal Analysis and Reliability of WIRE BONDED ECL		Original	PDF

AND8072 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
MC100EL91 Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16 100H646 Text: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE WIRE BONDED Device Failure Mechanisms For the plastic DIP, SOIC, TSSOP, PLCC, TQFP, and	Original	AND8072/D MC100EL91 MC100EPT25 MC100LVEP16 MC10LVEP16 100H646	PDF
3335 Abstract: MC100EL91 MC100EPT25 MC100LVEP16 MC10LVEP16 Text: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE WIRE BONDED Device Failure Mechanisms For the plastic DIP, SOIC, TSSOP, PLCC, TQFP, and	Original	AND8072/D r14525 3335 MC100EL91 MC100EPT25 MC100LVEP16 MC10LVEP16	PDF
MC100EL91 Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16 Text: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE WIRE BONDED Device Failure Mechanisms For the plastic DIP, SOIC, TSSOP, PLCC, TQFP, and	Original	AND8072/D r14525 MC100EL91 MC100EPT25 MC100LVEP16 MC10LVEP16	PDF
MC100EL91 Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16 E1651 Text: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE INTRODUCTION Normal operation of Integrated Circuits will cause electrical power, P, to be converted into heat by the die	Original	AND8072/D MC100EL91 MC100EPT25 MC100LVEP16 MC10LVEP16 E1651	PDF
MC100EL91 Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16 Text: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE INTRODUCTION Normal operation of Integrated Circuits will cause electrical power, P, to be converted into heat by the die	Original	AND8072/D MC100EL91 MC100EPT25 MC100LVEP16 MC10LVEP16	PDF
PS2360 Abstract: No abstract text available Text: MC100EP196 3.3VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further	Original	MC100EP196 EP195 EP196 r14525 MC100EP196/D PS2360	PDF
Untitled Abstract: No abstract text available Text: NB6L11 2.5V/3.3V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator. The device has the same pinout and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the	Original	NB6L11 NB6L11 LVEL11, LVEP11 NB6L11/D	PDF
NB6L16 Abstract: LVEL16 NB6L16D NB6L16DR2 NBSG16 6l16 Text: NB6L16 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/Driver/Translator Buffer The NB6L16 is a high precision, low power ECL differential clock or data receiver/driver/translator buffer. The device is functionally equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With	Original	NB6L16 NB6L16 LVEL16 NBSG16 NB6L16/D NB6L16D NB6L16DR2 6l16	PDF
H124 Abstract: LVEL17 MC10EPT20 Text: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal	Original	AN1672/D AN1568. r14525 H124 LVEL17 MC10EPT20	PDF
PS-4480 B Abstract: PS-4480 Text: MC100EP196 3.3VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further	Original	MC100EP196 EP195 EP196 r14525 MC100EP196/D PS-4480 B PS-4480	PDF
MC10EPT25 Abstract: MC10EPT22 MC10EPT24 MC10EPT23 MC10EPT21 ttl 7709 AND8072 HCT CMOS family characteristics AN1568 AND8020 Text: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective receiver in the LOW state. In contrast, ECL drivers source current in both HIGH and LOW states to the receiver).	Original	AN1672/D MC10EPT25 MC10EPT22 MC10EPT24 MC10EPT23 MC10EPT21 ttl 7709 AND8072 HCT CMOS family characteristics AN1568 AND8020	PDF
TND301 Abstract: AN1568 On Semiconductor Logic Data Code and Traceability Text: Application Note Listing ON Semiconductor pioneered the world of high performance clock and data management ICs with the invention of Emitter Coupled Logic in 1971. With that expertise comes a library of valuable information on designing high performance applications.	Original	AN1504 AN1568 AN1650 AND8001 AND8002 AND8003 AND8004 AND8020 AND8040 AND8072 TND301 On Semiconductor Logic Data Code and Traceability	PDF
PS-4480 Abstract: MC100 MC100EP196 MC100EP196FA MC100EP196FAR2 Text: MC100EP196 3.3VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further	Original	MC100EP196 MC100EP196 EP195 EP196 r14525 MC100EP196/D PS-4480 MC100 MC100EP196FA MC100EP196FAR2	PDF
EL90 Abstract: AN1568 AND8020 AND8066 AND8072 MC10EP195 H124 MC10EPT22 MC10EPT20 Text: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal	Original	AN1672/D AN1568. EL90 AN1568 AND8020 AND8066 AND8072 MC10EP195 H124 MC10EPT22 MC10EPT20	PDF

MC100 Abstract: MC100EP196 MC100EP196FA MC100EP196FAR2 Variable Resistor 3305 Text: MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar	Original	MC100EP196 MC100EP196 EP195 EP196 r14525 MC100EP196/D MC100 MC100EP196FA MC100EP196FAR2 Variable Resistor 3305	PDF