AF15 CC HEN VD Search Results

Contextual Info: ADVANCE INFORMATION ¡960 RP/RD I/O PROCESSOR AT 3.3 VOLTS 33 MHz, 3.3 Volt Version 80960RP 33/3.3 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960J F Core • Complies with PCI Local Bus Specification Revision 2.1 • 5 Volt P C I Signalling Environment

TC54512AP-15

Contextual Info: TOSHIBA TC54512AP-15.-20 TC54512AF-15.-20 SILICON STACKED GATE CMOS 65,536 WORD x 8 BIT ONE TIME PROGRAMMABLE READ ONLY MEMORY Description The TC54512AP/AF is a 65,536 word x 8 bit CMOS one tim e programm able read only m em ory m olded in a 28-pin plastic

af15 cc hen vd

Abstract: TC531000 571001
Contextual Info: TOSHIBA TC541000AP/AF-12, -15 TC541001AP/AF-12, -15 SILICON STACKED GATE CMOS 131,072 WORD x 8 BIT ONE TIME PROGRAMMABLE READ ONLY MEMORY Description The T C 5 4 1 0 0 0 A P /A F an d th e T C 5 4 1 0 0 1 A P /A F are 1 3 1 ,0 7 2 w o rd x 8 b it C M O S on e tim e p ro g ra m m a b le read only m em ories

quad relay board

Contextual Info: ¡960 Rx I/O Processor at 3.3 V 1.0 ABOUT THIS DOCUMENT This is the ADVANCE INFORMATION data sheet for the low-power 3.3 V versions of Intel’s i960® Rx I/O Processor family, including: • 80960RD 66/3.3 • 80960RP 33/3.3 Throughout this document, these fam ily members

L117As

Abstract: KIA1117AS 1117as KIA1117A
Contextual Info: KIA1117AS/AF00- SEM IC O N D U C TO R TECHNICAL DATA KIA1117AS/AF50 BIPOLAR LINEAR INTEGRATED CIRCUIT LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATOR The K IA 1117AS/AF x x is a Low Drop Voltage Regulator able to provide up to 1A o f output current, available even in adjustable

GIGABYTE G31

Abstract: SPARC v9 architecture BLOCK DIAGRAM gigabyte p31 187U UltraSPARC ii TP1030A
Contextual Info: S un M icro electro nics July 1997 U DATA SHEET l t r a S P A R C “-! First Generation SPARC v9 64-Bit Microprocessor With VIS D e s c r ip t io n The STP1030A, UltraSPARC-1, is a high-performance, highly-integrated superscalar processor implementing the SPARC V9 64-bit RISC architecture. The STP1030A is capable of sustaining the execution of up to four

TI 35X35 BGA 368 BGA

Abstract: EPF20K
Contextual Info: APEX 20K Programmable Logic Device Family November 1999. ver. 2.05 FeatU r6S D atasheet P re lim in a r y In fo rm a tio n • Industry's first program m able logic device PLD incorporating System -on-a-Program m able-Chip integration M ultiCore™ architecture integrating look-up table (LUT) logic,

RJP 3045

Abstract: Transistor z3p NP02 P104t str 1195 P022J I-CUBE iq P116C RP011 7805 v5
Contextual Info: M Ä ' I- C IQ Family Data Sheet u b e Features Description • Eight d evices ran gin g from 32 to 320 I / O Ports The IQ d evices are designed for use in sw itching and interconnect applications. In sw itching applications, these d evices are used to d ynam ically sw itch one or m ore signals. W hen

K1608

Abstract: asus mainboard diagram ND R433 asus Audi b5 z0123 asus notebook 401 asus schematic diagram z0121 lg r560 circuit diagram
Contextual Info:  ! " # Appendix B Circuit Diagrams * B This appendix has schematic circuit diagrams of the major parts of the notebook’s mainboard. Unless otherwise indicated, this reference has circuit diagrams for mainboard version 4.1. If the mainboard you are repairing is a different version, consult the manufacturer for the appropriate diagrams.

e/15-16M

Contextual Info: Preliminary Information AMDÌ1 A M D - 751" System Controller Data Sheet Publication #21910 Rev:D Issue Date: August 1999 H D25 752 5 OObaOBt. b l S 1999 Advanced Micro Devices, Inc. A ll rights reserved. T he c o n te n ts of th is d o cu m en t a re p ro v id ed in co n n ectio n w ith A d v an ced

qml-38535

Abstract: ASTM B 809 smd code AK6 59629851001QZC OP220 M38 smd
Contextual Info: REVISIONS LTR A DESCRIPTION DATE YR-MO-DA Table IA, Capacitance test - moved packages to show correct capacitance. Added conversion table for Y and Z package. Redrew case U figure 1 to correct row names. Made changes to Table IIA. ksr APPROVED 99-04-09 Raymond Monnin

DCM7 DIODE

Abstract: HD13S motorola mc55 DIODE CH71 82440MX mc60 speed controller 440MX STR M 6523 DCM7 MCEE
Contextual Info: intei 82443MX100 PCIset Datasheet • ■ Processor Host Bus Support — Optimized for the Intel mobile Pentium® II and the mobile Celeron processors at 100 MHz or 66 MHz — GTL+ Bus Driver Technology Integrated DRAM Support — 8 MB to 256 MB using 16-Mb,

Contextual Info: in te i 82443MX PCIset + Processor Host Bus Support — System Tim er based on 82C54 — O ptim ized fo r the Intel — Pentium ® II and m obile Celeron processors at 66 MHz Real Tim e C lock w / 256 Bytes Battery-backed RAM — X-bus Support for SIO, KBCX

P8021

Abstract: TL 949 "filtering database" h25g EPI LVDS rkg bh 16 D11A9 AE12A AF5A
Contextual Info: DATASHEET uu PM PMC-970861 IS S U E 5 PRELIMINARY PMC-Sierra, Inc. PM3370 OCTAL FAST ETHERNETSW ITCH PORT CONTROLLER WITH ADVANCED FEA TURES PM3370 8 X 10/100 MBIT/S ETHERNET SWITCH PORT CONTROLLER WITH ADVANCED FEATURES DATASHEET PRELIMINARY ISSUE 5: JANUARY 1999

AF2.5 din 74

Contextual Info: TNETX4090 ThunderSWITCH II 9-PORT 100-/1OOO-MBIT/S ETHERNET™ SWITCH • Single-Chip 100-/1000-Mbit/s Device • • Integrated Physical Coding Sublayer PCS Logic Provides Direct Interface to Gigabit Transceivers Port Trunking/Load Sharing for High-Bandwidth Interswitch Links

Contextual Info: TMX320C6201 DIGITAL SIGNAL PROCESSOR SPRS051A-JANUARY 1 9 9 7 -REVISED FEBRUARY 1997 1 600 MI PS @ 200 M H z F i v e - n s C y c l e T i me - E i g h t x 3 2 - B i t I n s tr uc t i on s / C y c l e - • Six A r i t hme t i c L ogi c Uni t s A L U s (32-/40-B i t)

Contextual Info: TMX320C6201 DIGITAL SIGNAL PROCESSOR SPRS051B - JANUARY 1997 - REVISED JUNE 1997 Highest Performance Fixed-Point Digital Signal Processor DSP : GGP 352-PIN BGA PACKAGE (BO TTO M V IE W ) I 26 o o o o o o o o o o o o o o o o o o o o o o o o o o - 1 600 MIPS @ 200 MHz

Contextual Info: 1.0 RS8234 Product Overview 1.1 Introduction The RS8234 Service Segmentation and Reassembly Controller Sem'ceSAR delivers a wide range of advanced ATM, AAL, and service-specific features in a highly integrated CMOS package. Some of the RS8234 service-level features provide system designers with

kbc 1070 nu

Abstract: KBC 1091 NU MXL 603 vcc3 1156 09 A52 infineon b 58 468 la intel 80 KBC 1098 NU smsc kbc 1091 KBC 1091- NU C5191 hcl p38 CIRCUIT diagram
Contextual Info: 5 4 MAX8743 1.8V & VCCP 3 2 TA6 SYSTEM BLOCK DIAGRAM P32 X 'TA L 14.318M MAX1541 (1.5 & VGACORE) P34 D 1 CPU Thermal Sensor P3 Intel CPU Yonah/Merom V C C _ C ORE GMCH_ V T T V C CA DISCHARGE P33 CK-GEN CK410M +3V +5V 479 Pins (uPGA) P2 D P3,4 VIDEO RAM

I-CUBE

Abstract: lp-032 IQX160-7PQ208 P124l P2G5 P1291
Contextual Info: i: * I- C u b IQX Family Data Sheet e m F eatures D e s c r ip t io n • SRAM-based, in-system programmable The IQX family of SRAM-based bit-oriented switching devices is • Switch Matrix manufactured using a 0.6|jm C M O S process. These devices offer clock speeds of up to 133 MHz and pin-to-pin delay as low

tdk ed29

Abstract: tdk ed28 C6200 UZ111 4h4 1 DMC TOOLS r3311 352-PIN AD17 C6201
Contextual Info: TMX320C6201 DIGITAL SIGNAL PROCESSOR SPRS051 - JANUARY 1997 VelociTI Advanced Very-Long Instruction Word VLIW Architecture: - Eight Independent Functional Units - Two 16-Bit Multipliers (32-Bit Results) - Six Arithmetic Logic Units (ALUs) (32-/40-Bit)

CMIP Common Management Information Protocol

Abstract: MAC110 ML53101
Contextual Info: Oki Semiconductor ML53101 8-Port Fast Ethernet Controller MAC8110— 10/100 Mbps 8-Port Media Access Controller 1. DESCRIPTION The ML53101 is an 8-Port Ethernet/Fast Ethernet Media Access Controller MAC8110 with eight media independent interfaces (Mils) on the Ethernet side. On the host side, a shared first-in first-out (FIFO)

Contextual Info: Preliminary PM Datasheet PMC-980618 PMC-Sierra, Inc. Issue 2 PM 73487 QRT 622 Mbps ATM Traffic Management Device PM73487 QRT 622 Mbps ATM Traffic Management Device DATASHEET Preliminary Issue 2: October 1998 m room'll DDEisaa 7^? n _ PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

ltsx e3

Contextual Info: data sheet PM PMC-1981224 ISSUE 6 r *• PMC-Sierra, Inc. PM7326 s / u n i a p e x A TM/PA CKET TRAFFIC MANAGER AND SWITCH PM7326 S/UNI - TM A PEX S/UNI APEX ATM/PACKET TRAFFIC MANAGERAND SWITCH DATA SHEET ISSUE 6: APRIL 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE