A7A1 Search Results

SPW 12w

Abstract: TMS380c16 RRU 32
Contextual Info: TMS380C26 NETWORK COMMPROCESSOR SPW S010A -APRIL 1992- R E V IS E D MARCH 1993 I • IEEE 802.5 and IBM Token-Ring Network Compatible • Low-Cost Host-Slave I/O Interface Option • IEEE 802.3 and Blue Book Ethernet™ Network Compatible • Selectable Host System-Bus Options

Contextual Info: EEPROM AS8E128K32 128K x 32 EEPROM PIN ASSIGNMENT EEPROM Memory Array Top View 66 Lead PGA AVAILABLE AS MILITARY SPECIFICATIONS • • (Pins 8, 21, 28, 39 are no connects on the PN package) SMD 5962-94585 MIL-STD-883 FEATURES OPTIONS • • 66 Lead PGA

Contextual Info: iPEM 2.4Gb SDRAM-DDR AS4DDR32M72PBG1 32Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR SDRAM Data Rate = 200, 250, 266, 333Mbps Package: • 208 Plastic Ball Grid Array PBGA , 16 x 23mm-1.0mm pitch 2.5V ±0.2V core power supply

Contextual Info: EEPROM AS8E512K8 512K x 8 EEPROM PIN ASSIGNMENT EEPROM Module Top View AVAILABLE AS MILITARY SPECIFICATIONS • • 32-Pin DIP & 32-Pin SOJ (CW) SMD 5962-93091 MIL-STD-883 FEATURES • • • • • • • • Access times of 150, 200, 250, and 300 ns

SMV512K32-SP

Contextual Info: SMV512K32-SP SLVSA21C – JUNE 2011 – REVISED OCTOBER 2011 www.ti.com 16-Mb RADIATION-HARDENED SRAM Check for Samples: SMV512K32-SP FEATURES • 1 • • • • • 20-ns Read, 13.8-ns Write Through Maximum Access Time Functionally Compatible With Commercial

DDR200

Abstract: DDR266A DDR266B IBMN612404GT3B IBMN612804GT3B IBMN62540 IBMN62580 128MB PC266
Contextual Info: IBMN612404GT3B IBMN612804GT3B 128Mb Double Data Rate Synchronous DRAM Preliminary Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency MHz * DDR266A (7N) DDR266B (75N) DDR200 (8N) 133 143 100 133 100 125 * Values are nominal (exact tCK should be used).

NT5DS8M16FS-5T

Abstract: NT5DS8M16FS-6K NT5DS8
Contextual Info: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T

ba1s

Contextual Info: IS43LR32400E Advanced Information 1M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43LR32400E is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The address lines are multiplexed with the Data

Nanya nt5ds8m16fs

Abstract: NT5DS8M16FS NT5DS8M16FT-5TI NT5DS8M16FS-5T DDR333 DDR400 NT5DS8M16 NT5DS8M16FT-6KI NT5DS8M16FT
Contextual Info: NT5DS8M16FT-5TI NT5DS8M16FS-5TI NT5DS8M16FT-6KI NT5DS8M16FS-6KI 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8

NT5DS8M16FS-5T

Abstract: NT5DS8M16FS-6K NT5DS8M16 NT5DS8M16FS
Contextual Info: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T

NT5DS16M16BF-6K

Abstract: NT5DS32M8BT NT5DS16M16BT-6K NT5DS16M16BT NT5DS64M4BT NT5DS32M
Contextual Info: NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Features • Data mask DM for write data • DLL aligns DQ and DQS transitions with CK transitions

DDR200

Abstract: DDR266A DDR266B IBMN62540 IBMN625404GT3B IBMN62580 IBMN625804GT3B
Contextual Info: IBMN625404GT3B IBMN625804GT3B 256Mb Double Data Rate Synchronous DRAM Preliminary Features CAS Latency and Frequency CAS Latency Maximum Operating Frequency MHz * DDR266A (7N) DDR266B (75N) DDR200 (8N) 133 143 100 133 100 125 2 2.5 * Values are nominal (exact tCK should be used).

R14 P1F

Abstract: N-333 PP7F 1BE3 P53 transistor A1-U1-U17-A17 3LH30 zz12
Contextual Info: TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CF26AXBG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. TMP92CF26A

IS43LR16640A

Abstract: IS43LR16640A-5BLI IS43LR16640A-6BLI IS46LR16640A-5BLA1 IS43LR16640A-6BL
Contextual Info: IS43/46LR16640A Advanced Information 16M x 16Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR16640A is 1,073,741,824 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 16,777,216 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted

Contextual Info: MAY 4 1992 w .- . IMP23L128 IMP23L256 IMP23L512 VERY LOW POWER 23000 Series ROMS IMP23L100 IMP23L101 IMP23L208 LOW POWER/HIGH PERFORMANCE CMOS ROMS Features • Six JEDEC Standard Versions: IMP23L128 IMP23L256 IMP23L512 IMP23L100 IMP23L101 IMP23L208

M28W320BB

Abstract: M28W320BT
Contextual Info: M28W320BT M28W320BB 32 Mbit 2Mb x16, Boot Block 3V Supply Flash Memory FEATURES SUMMARY • SUPPLY VOLTAGE Figure 1. Packages – VDD = 2.7V to 3.6V Core Power Supply – VDDQ= 1.65V to 3.6V for Input/Output – VPP = 12V for fast Program (optional) ■

79LV0832

Contextual Info: 79LV0832 8 Megabit 256K x 32-Bit Low Voltage EEPROM MCM DESCRIPTION: • 256k x 32-bit EEPROM MCM • RAD-PAK radiation-hardened against natural space radiation • Total dose hardness: - >100 krad (Si) - Dependent upon orbit • Excellent Single event effects

DDR200

Abstract: DDR266A HYB25D256400AT-7 HYB25D256400AT-8 HYB25D256800AT-7 HYB25D256800AT-8 TSOP66
Contextual Info: HYB25D256400/800AT 256-MBit Double Data Rata SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency MHz DDR266A DDR200 -7 -8 133 100 143 125 • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted

STLC5411

Abstract: DIP28 PLCC44 ST5421 ST5451 STLC5411FN STLC5411P
Contextual Info: STLC5411 2B1Q U INTERFACE DEVICE GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIONS MEETS OR EXCEEDS ANSI U.S. AND ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE HCMOS3A SGS-THOMSON ADVANCED

Midcom CR 0090

Contextual Info: D A TA S H E E T JUNE 1999 LXT359 Revision 2.1 Integrated T1 LH /SH Transceiver for D S1/DSX-1/CSU o r NTU /ISD N P R I Applications General Description Features The LXT359 is a T1 Primary rate, combination transceiver for T1 long and short-haul applications. It operates over 22

GC102

Abstract: 8088 motherboard schematics ASC 8.000MHz crystal oscillator cpu 416-2 DP CQA03 coa030 sd 7406 ero 1818 74ALS245 TI HA 7406
Contextual Info: G-TUO -CE} INC D 5 D E I 3 7 7 7 4 7 S OGGOOt ,4 S I i i u i u i 7v ; c i o 2 12/16MHz PC/AT Compatible C h ip set Features Description • Highly Integrated PC/AT Com­ patible Three Chip Set. The GC101/GC102 is a fully IBM PC/AT compatible chip set support­

A48P4616

Abstract: DDR333 DDR400
Contextual Info: A48P4616 Preliminary 16M X 16 Bit DDR DRAM Document Title 16M X 16 Bit DDR DRAM Revision History Rev. No. 0.0 History Issue Date Remark Initial issue September 5, 2005 Preliminary Preliminary September, 2005, Version 0.0 AMIC Technology, Corp. A48P4616 Features

400F

Abstract: K9F4008W0A K9F4008W0A-TCB0 K9F4008W0A-TIB0 KM29W040AIT KM29W040AT k9f4008w0atcb0
Contextual Info: K9F4008W0A-TCB0, K9F4008W0A-TIB0 FLASH MEMORY Document Title 512K x 8 bit NAND Flash Memory Revision History Revision No. History Draft Date Remark Preliminary Initial issue. April 10th 1998 1.0 1. Changed Operating Voltage 2.7V ~ 5.5V → 3.0V ~ 5.5V July 14th 1998

Contextual Info: AT29C01OA Features • • • Fast Read Access Tim e - 70 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram Erase and Program 1024 Sectors (128 bytes/sector) Internal Address and Data Latches for 128-Bytes Two 8 KB Boot Blocks with Lockout