A10A11 Search Results

Contextual Info: TYPES SN54ALS677, SN54ALS678. SN74ALS677, SN74ALS678 ADDRESS COMPARATORS D 2 6 6 1 , J U N E 1 9 8 2 — R E V IS E D D E C E M B E R 1 9 8 3 S N 54A LS 677 . . . JT PACKAGE SN 74A LS 677 . . . .NT PACKAGE TOP VIEW • A L S 6 7 7 is a 16 -b it to 4-B it Comparator w ith Enable

Sony IMX 183

Abstract: Sony sony cmos sensor imx 178 Sony imx 214 Sony ImX 252 sony cmos sensor imx 226 Sony IMX 219 CMOS Sony "IMX 219" CMOS sony IMX 322 cmos sony cmos sensor imx 185
Contextual Info: i.MX 6Solo/6DualLite Applications Processor Reference Manual Document Number: IMX6SDLRM Rev. 1, 04/2013 i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 1, 04/2013 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1

Contextual Info: March 1994 DATA SHEET_ HM 65764 8 Kx 8 HIGH SPEED CMOS SRAM FEATURES . . . . 300 AND 600 MILS WIDTH PACKAGE . TTL COMPATIBLE INPUTS AND OUTPUTS . ASYNCHRONOUS . CAPABLE OF WITHSTANDING GREATER THAN 2000 V ELECTROSTATIC DISCHARGE

2MX16X4

Abstract: IS42S32400AL
Contextual Info: IS42S81600AL, IS42LS81600AL IS42S16800AL, IS42LS16800AL IS42S32400AL, IS42LS32400AL 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT LOW-POWER SYNCHRONOUS DRAM ISSI PRELIMINARY INFORMATION SEPTEMBER 2003 • Clock frequency: 133, 100, MHz OVERVIEW ISSI's 128Mb Low - Power Synchronous DRAM achieves

W641GG2KB

Abstract: gddr3 schematic WBGA-136 W641GG2
Contextual Info: W641GG2KB 1-Gbit GDDR3 Graphics SDRAM Table of Contents 1. GENERAL DESCRIPTION . 6 2. FEATURES . 7

HM628512

Contextual Info: HM628512 Series 524288-word x 8-bit High Speed CMOS Static RAM HITACHI ADE-203-236F Z Rev. 6.0 Jun. 9, 1995 Description The Hitachi HM628512 is a 4-Mbit static RAM organized 5 12-kword x 8-bit. It realizes igher density, higher performance and low power consumption by employing 0.5 |J.m Hi-CMOS process technology. The device,

POWER COMMAND HM 1211

Abstract: power generation POWER COMMAND HM 1211 6331-1 gddr3 schematic HYB18T256324F-20 infineon sgram
Contextual Info: Data Sheet, Rev. 1.11, April 2005 HYB18T256324F–16 HYB18T256324F–20 HYB18T256324F–22 256-Mbit GDDR3 DRAM [600MHz] RoHS compliant Memory Products N e v e r s t o p t h i n k i n g . Edition 04-2005 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

Contextual Info: 13E D I TSOSBID □0G04t.l VITELIC CORP V s\ - Z 3 'O VITELIC ^ V61C67 FAMILY HIGH PERFORMANCE LOW POWER 16K x 1 BIT CMOS STATIC RAM Features Description • High Speed • Maximum access time of 2 5 /3 5 /4 5 /5 5 /7 0 ns The V61C67 is a high speed, low power, 16,384word by 1-bit CMOS static RAM fabricated using

25x10

Abstract: CI 576
Contextual Info: MITSUBISHI LSIs SDRAM Rev.3.1 Nov.'01 M2L64S40DWG -6, -6L,-7,-7L (4-BANK x 1,048,576-WORD x 16-BIT) 64M Low Power Synchronous DRAM Some of contents are described for general products and are subject to change without notice. DESCRIPTION M2L64S40DWG is a 4-bank x 1,048,576-word x 16-bit, low power synchronous DRAM, with1.8V

Contextual Info: 27C256T 256K 32K x 8-Bit OTP EPROM A5-A9 1024 x 1022 Memory Matrix x-Decoder NC A12-A14 A12-A16 I/O0 Y- Gating Input Data Control I/O 7 I/O15 Y - Decoder 27C256T CE OE A0-A4 A10-A11 PGM VCC VPP VSS H H : High Threshhold Inverter FEATURES: DESCRIPTION: • 32K x 8-bit OTP EPROM organization

Contextual Info: CHB/CHC Series How to order CH Ref. order * * * * * * * * * * * * CONNECTOR FAMILY Contact arrangement Two rows Three rows B C Connector size Two rows: 017-029-033-041-053-065-072-084-096-120 Three rows: 026-044-062-080-098-108-126-144 Without contact: 000

hypertac connector insertion tools

Abstract: HYPERTAC CONTACT PIN a17 JN1123 HYPERTAC PIN CHC144 Hypertac connector
Contextual Info: CHB CHC PCB Connectors January 2005 ISSUE 1.0 • ENGLISH This datasheet has been downloaded from http://www.digchip.com at this page HYPERTAC CONTACT wire sleeve before insertion of pin pin partially inserted into sleeve pin completely inserted into sleeve

HYB18T256324

Contextual Info: Data Sheet, Rev. 1.11, April 2005 HYB18T256324FL22 HYB18T256324FL25 256-Mbit GDDR3 DRAM RoHS compliant Memory Products N e v e r s t o p t h i n k i n g . Edition 04-2005 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany

HYB18H512321AF-14

Contextual Info: Data Sheet, Rev. 1.30, Feb. 2005 HYB18H512321AF–14 HYB18H512321AF–16 HYB18H512321AF–20 512-Mbit GDDR3 Graphics RAM [700 MHz] Green Product Memory Products N e v e r s t o p t h i n k i n g . Edition 2005-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

MICRON gddr3

Abstract: GDDR3 SDRAM 256Mb gddr3 FBGA DDR3 x32 35w4 MT44H8M32F2FW-16 32x4 BA1T10 marking R810
Contextual Info: ADVANCE‡ 256Mb: x32 GDDR3 SDRAM GRAPHICS DDR3 SDRAM MT44H8M32 – 2 MEG x 32 x 4 BANKS For the latest data sheet, please refer to the Micron Web site: www.micron.com/datasheets Features • • • • • • • • • • • • • • • • •

Contextual Info: QS316245 PRELIMINARY Q High-Speed CMOS QuickSwitch 16-Bit Widebus Compatible Bus Switches FEATURES/BENEFITS QS316245 DESCRIPTION 5 switches connect inputs to outputs Direct bus connect Pin compatible with FCT16245 Flowthrough pinout for easy layout Zero propagation delay

PD7507C

Abstract: PD7507 MPD7507 PD7508 P7q-P73 nec 7508 eprom 2716 UPD7227 D75CG08 75CG08E
Contextual Info: %Tt7{2 //P D 7 5 0 7 /0 8 4 -B it, Single-C hip CMOS M icrocom puters NEC Electronics Inc. D e scrip tio n F e a tu re s The /^PD7507 and //PD7508 4-bit, single-chip CM OS microcomputers have the//PD7500 series architecture. The subroutine stack is implemented in RAM for

ic programmer

Contextual Info: s ie b S D llS b NATL S E MI CO ND 00b52fc.l 33T «NSC3 MEMORY gH National SLA Semiconductor ~ r- NMC27C32B 32,768-Bit (4096 x 8) CMOS EPROM General Description Features The NMC27C32B is a 32k UV erasable and electrically re­ programmable CMOS EPROM, ideally suited for applica­

D4001

Contextual Info: 27C1512T 512Kb 32K x 16-bit OTP EPROM MCM A5 A9 X-Decoder 1024 x 512 Memory Matrix A12 A16 I/O0 Input Data Control I/O7 Y-Gating Y-Decoder CE OE A0-A4 A10-A11 PGM Memory VCC VPP H : High Threshold Inverter H VSS Logic Diagram FEATURES: DESCRIPTION: • 32K x 16 Bit OTP EPROM organization

EPR48

Abstract: LCD 2 x 16 ia87
Contextual Info: r = 7 Ä T # S G S - T H O M S O N R Æ Œ (ô m i(O T (ô K S S T 1 8 9 3 0 /3 1 DIGITAL SIGNAL PR O C ESSO R • 80 ns INSTRUCTION CYCLE TIME ‘ (1.2 (i CMOS technology) ■ PARALLEL HARVARD ARCHITECTURE ■ SEPARATED PROGRAM AND DATA BUSES ■ THREE DATA BUSES STRUCTURE

st z 426

Contextual Info: electronic June 1992 HM 65787 HI-REL DATA SHEET_ 64 k x 1 HIGH SPEED CMOS SRAM FE A T U R ES . FAST ACCESS TIME : 25/35 Z45/55 ns . LOW POWER CONSUMPTION ACTIVE : 320 mW typ STANDBY : 75 mW (typ) DATA RETENTION : 0.8 nW (typ) . TTL COMPATIBLE INPUTS AND OUTPUTS

Contextual Info: Preliminary HM62D932 Series 32,768-Word x 9-Bit High Speed CMOS Static Ram with Address Latch • FEATURES • High speed: fast access time 15/20 ns max. • Low Power Standby: 15nW (typ.) (L-version) Operation: 350mW (typ.) • Single 5V supply • Address Latch

FLASH MEMORY 29F

Abstract: IC 7107 Pin diagram 29f flash 29F 128 16 S29F010 TMS29F010JL4
Contextual Info: TMS29F010 1 048 576-BIT FLASH/BLOCK ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMJS01OA • Organization 128K x 8 or 4 Blocks of AUGUST 1990 — REVISED DECEMBER 1990 N and J P ackages Top View • HVCMOS Technology NC [ , A16f 2 A15[ 3 • All Inputs/Outputs TTL Compatible

HYB18H512321AF-12

Abstract: gddr3 schematic BCX10
Contextual Info: Data Sheet, Rev. 1.73, Aug. 2005 HYB18H512321AF–12/14/16/20 HYB18H512321AFL14/16/20 512-Mbit GDDR3 Graphics RAM RoHS compliant Memory Products N e v e r s t o p t h i n k i n g . Edition 2005-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53,