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    SN74LV32A Search Results

    SN74LV32A Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LV32ANSR Texas Instruments Quadruple 2-Input Positive-OR Gates 14-SO -40 to 125 Visit Texas Instruments Buy
    SN74LV32ARGYR Texas Instruments Quadruple 2-Input Positive-OR Gates 14-VQFN -40 to 125 Visit Texas Instruments Buy
    SN74LV32ADR Texas Instruments Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LV32APWRG4 Texas Instruments Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV32ATPWRG4Q1 Texas Instruments Automotive Catalog Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 105 Visit Texas Instruments Buy
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    SN74LV32A Price and Stock

    Rochester Electronics LLC SN74LV32AD

    IC GATE OR 4CH 2-INP 14SOIC
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    Rochester Electronics LLC SN74LV32ADR

    IC GATE OR 4CH 2-INP 14SOIC
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    Rochester Electronics LLC SN74LV32ADBR

    IC GATE OR 4CH 2-INP 14SSOP
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    Rochester Electronics LLC SN74LV32APW

    IC GATE OR 4CH 2-INP 14TSSOP
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    Rochester Electronics LLC SN74LV32ADGVR

    IC GATE OR 4CH 2-INP 14TVSOP
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    SN74LV32A Datasheets (108)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN74LV32A Texas Instruments Quadruple 2-Input Positive-OR Gates Original PDF
    SN74LV32A Texas Instruments QUADRUPLE 2-INPUT POSITIVE-OR GATES Original PDF
    SN74LV32AD Texas Instruments Quadruple 2-Input Positive-OR Gates Original PDF
    SN74LV32AD Texas Instruments Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85 Original PDF
    SN74LV32AD Texas Instruments SN74LV32 - Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85 Original PDF
    SN74LV32AD Texas Instruments QUADRUPLE 2-INPUT POSITIVE-OR GATES Original PDF
    SN74LV32ADB Texas Instruments QUADRUPLE 2-INPUT POSITIVE-OR GATES Original PDF
    SN74LV32ADBLE Texas Instruments SN74LV32 - Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85 Original PDF
    SN74LV32ADBLE Texas Instruments Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85 Original PDF
    SN74LV32ADBLE Texas Instruments QUADRUPLE 2-INPUT POSITIVE-OR GATES Original PDF
    SN74LV32ADBR Texas Instruments SN74LV32 - Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85 Original PDF
    SN74LV32ADBR Texas Instruments Quadruple 2-Input Positive-OR Gates Original PDF
    SN74LV32ADBR Texas Instruments Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85 Original PDF
    SN74LV32ADBR Texas Instruments QUADRUPLE 2-INPUT POSITIVE-OR GATES Original PDF
    SN74LV32ADBRE4 Texas Instruments SN74LV32 - Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85 Original PDF
    SN74LV32ADBRE4 Texas Instruments Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85 Original PDF
    SN74LV32ADBRE4 Texas Instruments Quadruple 2-Input Positive-OR Gates Original PDF
    SN74LV32ADBRG4 Texas Instruments SN74LV32 - Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85 Original PDF
    SN74LV32ADBRG4 Texas Instruments Quadruple 2-Input Positive-OR Gates 14-SSOP -40 to 85 Original PDF
    SN74LV32ADE4 Texas Instruments SN74LV32 - Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85 Original PDF

    SN74LV32A Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV32AĆEP QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCLS565A − JANUARY 2004 − REVISED MAY 2004 D Controlled Baseline D D D D D D D Typical VOLP Output Ground Bounce − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 105°C


    Original     		SN74LV32AÄ SCLS565A PDF

    SN54LV32A

    Abstract: SN74LV32A
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385C – SEPTEMBER 1997 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV32A, SN74LV32A SCLS385C MIL-STD-883, SN54LV32A SN74LV32A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C


    Original     		SN74LV32A-EP SCLS565B PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV32A, SN74LV32A SCLS385J 000-V A114-A) A115-A) SN54LV32A PDF

    LV32A

    Abstract: No abstract text available
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385E – SEPTEMBER 1997 – REVISED AUGUST 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y


    Original     		SN54LV32A, SN74LV32A SCLS385E 000-V A114-A) A115-A) SN54LV32A LV32A PDF

    A115-A

    Abstract: C101 SN54LV32A SN74LV32A
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV32A, SN74LV32A SCLS385J SN54LV32A A115-A C101 SN54LV32A SN74LV32A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV32AĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCLS516C − JULY 2003 − REVISED FEBRUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		SN74LV32AQ1 SCLS516C MIL-STD-883, PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV32A, SN74LV32A SCLS385J PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y


    Original     		SN54LV32A, SN74LV32A SCLS385G 000-V A114-A) A115-A) SN54LV32A SN74LV32A, PDF

    SN74LV32A

    Abstract: SN74LV32A-Q1 SN74LV32ATPWRG4Q1 SN74LV32ATPWRQ1
    Text: SN74LV32A-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCLS516C − JULY 2003 − REVISED FEBRUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		SN74LV32A-Q1 SCLS516C MIL-STD-883, SN74LV32A SN74LV32A-Q1 SN74LV32ATPWRG4Q1 SN74LV32ATPWRQ1 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D Ioff Supports Partial-Power-Down Mode D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 11


    Original     		SN54LV32A, SN74LV32A SCLS385J SN54LV32A PDF

    A115-A

    Abstract: C101 SN54LV32A SN74LV32A 74LV32a
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV32A, SN74LV32A SCLS385J SN54LV32A A115-A C101 SN74LV32A 74LV32a PDF

    A115-A

    Abstract: C101 SN54LV32A SN74LV32A
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV32A, SN74LV32A SCLS385J SN54LV32A A115-A C101 SN74LV32A PDF

    A115-A

    Abstract: C101 SN54LV32A SN74LV32A 74LV32A
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385D – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		SN54LV32A, SN74LV32A SCLS385D SN54LV32A 000-V A114-A) A115-A) A115-A C101 SN54LV32A SN74LV32A 74LV32A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES S C L S 3 8 5 A - S E P TE M B E R 1997 - R EVISED A P R IL 1998 EP/C Enhanced-Performance Implanted CMOS Process SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)


    OCR Scan     		SN54LV32A, SN74LV32A MIL-STD-883, SN54LV32A SN74LV32A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C


    Original     		SN74LV32A-EP SCLS565B PDF

    LV32

    Abstract: No abstract text available
    Text: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C


    Original     		SN74LV32A-EP SCLS565B LV32 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV32A-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCLS516C − JULY 2003 − REVISED FEBRUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		SN74LV32A-Q1 SCLS516C MIL-STD-883, PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV32AĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS516B − JULY 2003 − REVISED MAY 2004 D Qualification in Accordance With D D D D D D D D Supports Mixed-Mode Voltage Operation on AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control


    Original     		SN74LV32AQ1 SCLS516B AEC-Q100 MIL-STD-883, PDF

    A115-A

    Abstract: C101 SN54LV32A SN74LV32A
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV32A, SN74LV32A SCLS385J SN54LV32A A115-A C101 SN54LV32A SN74LV32A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C


    Original     		SN74LV32A-EP SCLS565B PDF

    SN54LV32A

    Abstract: SN74LV32A
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385B – SEPTEMBER 1997 – REVISED NOVEMBER 1999 D D D D D EPIC Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV32A, SN74LV32A SCLS385B MIL-STD-883, SN54LV32A SN54LV32A SN74LV32A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C


    Original     		SN74LV32A-EP SCLS565B PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y


    Original     		SN54LV32A, SN74LV32A SCLS385G 000-V A114-A) A115-A) SN54LV32A PDF