271062
Abstract: M82965
Text: in te i M82965 FAULT TOLERANT BUS EXTENSION UNIT Military Multiprocessor Support — Connect up to 32 Processor and Memory Modules In a Single System Message Passing — Supports Interagent Communication — Redundant Error Reporting Network Multiple Bus Support with No External
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bx-upi
Abstract: 271062 "FRC"
Text: M W Â K K S E O ßiO IFÜ K lM lÄ TD ^ in te * M82965 FAULT TOLERANT BUS EXTENSION UNIT Military Multiprocessor Support — Connect up to 32 Processor and Memory Modules In a Single System Multiple Bus Support with No External Logic — Connect up to Four 32-Bit Buses for
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M82965
bx-upi
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AP 309
Abstract: lad7b10 voter 80960MC M82965 MG82965 intel DOC
Text: M W A N S E in te i M82965 FAULT TOLERANT BUS EXTENSION UNIT Military Multiprocessor Support — Connect up to 32 Processor and Memory Modules in a Single System Multiple Bus Support with No External Logic — Connect up to Four 32-Bit Buses for High-Bandwidth Access to
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M82965
32-Bit
M8296S
AP 309
lad7b10
voter
80960MC
M82965
MG82965
intel DOC
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80960MC
Abstract: AC GENERATOR 0011B M8259A M82965
Text: Memory and I/O Interface Using the BXU CHAPTER 9 MEMORY AND I/O INTERFACE USING THE BXU The M82965 B X U provides many features that enhance high-performance multiprocessor designs. This chapter outlines approaches to design memory and I/O systems in a multiprocessor design thdt
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M82965
80960MC
M8259A,
AC GENERATOR
0011B
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processor
Abstract: 80960MC M82965
Text: Processor Management and Initialization g CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION This chapter describes the facilities for initializing and managing the operation of the 80960MC processor. Included is an overview of the processor-management facilities and a
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processor
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80960MC
Abstract: M82965
Text: Multiple-Processor Operation 75 CHAPTER 15 MULTIPLE-PROCESSOR OPERATION This chapter presents several features of the processor that support multiprocessor systems. Included are discussions of external IAC messages, high-level process management facilities,
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80960MC
Abstract: INTEL 80960 pipeline architecture M82965 80960
Text: Introduction to the 80960 Architecture 2 CHAPTER 2 INTRODUCTION TO THE 80960 ARCHITECTURE This chapter provides an overview of the architecture on which the 80960MC processor is based. A NEW 32-BIT ARCHITECTURE FROM INTEL The 80960MC processor is the military-grade member of a new family of processors from
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80960MC
Abstract: AD30 M82965 FFFC0000
Text: Initialization CHAPTER 14 INITIALIZATION This chapter describes the hardware requirements for initializing the 80960MC processor and the BXU in a fault-tolerant system design. The basic minimum initialization requirements are described, as well as some of the available options. The exact initialization procedure depends on the type of
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FFFC0000
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Embedded Applications Handbook 270646
Abstract: intel Multibus i handbook 230843 embedded controller handbook Mohawk 80960MC 80960 1989 intel I860 processor 270646 multibus II architecture specification
Text: 80960MC Hardware Designer’s Reference Manual June, 1989 Order Number: 271079-002 intei LITERATURE T o o rd er Intel Literature or obtain literature pricing inform ation in the U .S. and C anad a call or w rite Intel Literature Sales. In Europe and other international locations, please contact your local sales office or
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80960MC
Embedded Applications Handbook 270646
intel Multibus i handbook
230843
embedded controller handbook
Mohawk
80960 1989
intel I860 processor
270646
multibus II architecture specification
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0011B
Abstract: 0040H 80960MC M82965
Text: Advanced Processor Bus 7 CHAPTER 7 ADVANCED PROCESSOR BUS Efficient bus utilization is essential in a multiprocessing system. A simple and efficient approach to building an 80960MC processor interconnect system is to use the Advanced Processor bus AP-bus
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32-bit
0011B
0040H
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interlace parity
Abstract: 80960MC M82965
Text: Confinement Areas/ Detection Mechanisms 77 CHAPTER 11 CONFINEMENT AREAS/DETECTION MECHANISMS The first step toward fault-tolerant design is to detect and isolate the error. This chapter describes the details of the 80960 architecture confinement areas and the associated detection mechanisms.
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interlace parity
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