LSA2000 Search Results

GFT1811A

Abstract: 74181 alu 74181 alu 74181 logic Alu 183 32 bit carry select adder
Contextual Info: Table of Contents - Part II The follow ing megafunctions are available in the LL7000 Series, LL9000 Series, and LSA2000 Series of channeled gate array products. M ost of these are also available in the LL5000 Series of gate arrays. M egafunction Name Type

Contextual Info: GFS2020A GFS2020A GFS2020A 1 6 X 4 CAM WITHOUT MASK GENERAL DESCRIPTION: THE GFS2020A MEGAFUNCTION IS A 16-WORD BY 4-BIT CONTENT ADDRESSABLE MEMORY CAM . THIS MEGAFUNCTION IS FUNCTIONALLY IDENTICAL TO THE FAIRCHILD 100142 EXCEPT THAT IT HAS SIXTEEN WORDS INSTEAD OF FOUR AND IT HAS NO MASK FUNCTION. FOR A DETAILED

amd 2900

Abstract: Y122 Am2910 y322
Contextual Info: GFAOIOIA GFAOIOIA GFAOIOIA MICROPROGRAM CONTROLLER GENERAL DESCRIPTION: THE GFAOIOIA IS A 5-DEEP STACK, 16-BIT WIDE ADDRESS SEQUENCER WHICH CONTROLS THE SEQUENCE OF EXECUTION OF THE MICRO-INSTRUCTIONS. IT IS DESIGNED TO BE FULLY COMPATIBLE WITH THE AM2910 EXCEPT WHEN ILLEGAL OPERATIONS ARE PERFORMED ON THE STACK

Contextual Info: GFS2010A GFS2010A GFS2 01OA 8 X 4 CAM WITHOUT MASK G E N ERAL D E S C R I P T I O N : THE GFS2010A MEGAFUNCTION IS AN 8-WORD BY 4-BIT CONTENT ADDRESSABLE MEMORY CAM . THIS MKGAFUNCTION IS FUNCTIONALLY IDENTICAL TO THE FAIRCHILD 100142 EXCEPT THAT IT HAS EIGHT WORDS INSTEAD OF FOUR AND IT HAS NO MASK FUNCTION. FOR A DETAILED

LSA2000

Abstract: 74181 alu
Contextual Info: GFT1813A GFT1813A GFT1813A 32-BIT ALU GENERAL DESCRIPTION: THE GFT1813A MEGAFUNCTION IS LOGICALLY IDENTICAL TO THE TI 74181, EXCEPT IT OPERATES ON TWO 32-BIT WORDS. THE GPT1813A ARITHMETIC LOGIC UNIT ALU PERFORMS 16 LOGICAL OPERATIONS, AND USES A 32-BIT FAST CARRY-SELECT ADDER TO PERFORM 16

Contextual Info: GFB0220A GFB0220A GFB0220A 16-BIT CARRY-SELECT ADDER GENERAL D E S C R I P T I O N : THE GFB0220A USES A FAST CARRY-SELECT ALGORITHM TO PERFORM AN ADDITION OF TWO 16-BIT NUMBERS. PIN DIAGRAM: GFB0220A •GATES USED » 287 -AREA USED - 376 GATE LOCATIONS •PROPAGATION DELAY « 28 NS

TRANSISTOR a31

Abstract: magnitude comparator Transistor B29 transistor A19 P
Contextual Info: GFC2200A GFC2200A 32-BIT MAGNITUDE COMPARATOR GFC2200A GENERAL DESCRIPTION: THE GFC2200A IS A MAGNITUDE COMPARATOR. IT COMPARES TWO 32-BIT BINARY NUMBERS AND YIELDS THREE OUTPUTS {A>B, A<B„ AND A-B . PIN DIAGRAM: GFC2200A - GATES USED - 34 8 - AREA USED - 379 GATE

through data 4 a

Contextual Info: GFS0510A GFS0510A GFS0510A 16 X 4 FIFO FIRST-IN FIRST-OUT GENERAL DESCRIPTION: THE GFS0510A MEGAFUNCTION IS A 16 X 4 FIFO (FIRST-IN FIRST-OUT) . IT HAS SEPARATE READ (RDN) AND WRITE (WRN) CLOCKS WHICH ARE COMPLETELY INDEPENDENT <CAN BE ASYCHRONOUS) . THIS FIFO USES A "FALL-THROUGH“ ALGORITHM IN WHICH

P08 transistor

Abstract: 8x8 booth multiplier
Contextual Info: GFB2000A GFB2000A GFB2000A 8X8 2 'S COMPLEMENT MULTIPLIER GENERAI. DESCRIPTION: THE GFB2000A MEGAFUNCTION 15 AN 8-BY-8 2 'S COMPLEMENT MULTIPLIER WHICH GENERATES A 16-BIT PRODUCT. BY USING A MODIFIED BOOTH ALGORITHM, THIS MEGAFJNCTION GIVES A REASONABLE SPEED AND GATE COUNT.

Am29501

Abstract: BM05 05GN amd 2900 transistor BMO 123
Contextual Info: GFA5010A GFA5010A GFA5010A MULTI-PORT PIPELINED PROCESSOR GENERAL DESCRIPTION: THE GFA5010A IS DESIGNED TO BE FULLY COMPATIBLE WITH THE AM29501 BYTE—SLICE MULTI-PORT PIPELINED PROCESSOR, EXCEPT THAT THE I/O'S ARE DIFFERENT SEE PAGE 2 OF 4 FOR A DESCRIPTION OF THE ENHANCEMENTS TO THE AM29501 . FOR A DETAILED

5 pin ic ARB

Abstract: amd 2900
Contextual Info: GFA0040A GFA0040A GFA0040A STATUS AND SHIFT CONTROL UNIT GENERAL DESCRIPTION : THE GFA004 0A IS DESIGNED TO BE FUNCTIONALLY IDENTICAL TO THE AM2904 f ALTHOUGH THE I/O'S ARE DIFFERENT SEE PAGE 2 OF 3 FOR THE ENHANCEMENTS TO THE AM2904 . FOR A DETAILED FUNCTIONAL DESCRIPTION SEE THE AMD 2900 DATA BOOK.

transistor p06

Abstract: P08 transistor p023 transistor
Contextual Info: GFB2010A GFB2010A GFB2010A 12 X 12 2 1S COMPLIMENT MULTIPLIER GENERAL DESCRIPTION: THE GFB2010A MEGAFUNCTION IS A 12 X 12 2 1S COMPLEMENT MULTIPLIER WHICH GENERATES A 24-BIT PRODUCT. BY USING A MODIFIED BOOTH ALGORITHM, THIS MEGAFUNCTION GIVES A REASONABLE SPEED AND GATE COUNT.

16-bit alu

Abstract: functional diagram of ALU
Contextual Info: GFB1020A GFB1020A 16-BIT ALU GFB1020A GENERAL DESCRIPTION: THE GFB1020A MEGAFUNCTION IS A 16-BIT VERSION OF THE FAIRCHILD 100181 ALU, EXCEPT FOR THE ABSENCE OF THE OUTPUT LATCHES AND THE LATCH ENABLE SIGNAL. THE GFB1020A ARITHMETIC LOGIC UNIT ALU PERFORMS 4 BINARY, 4 BCD, AND 8 LOGIC OPERATIONS ON

s16 transistor

Abstract: transistor bl 187 c14 c13
Contextual Info: GFB0600A GFB0600A GFB0600A 3-PORT 16-BIT CARRY-SELECT ADDER GENERAL DESCRIPTION: THE GFB0600A IS A 3-PORT 16-BIT CARRY-SELECT ADDER. IT USES A FAST CARRYSELECT ALGORITHM TO PERFORM ADDITION OF THREE 16-BIT NUMBERS. PIN DIAGRAM: GFB0600A - GATES USED - 396

Contextual Info: GFC2100A GFC2100A GFC2100A 16-BIT MAGNITUDE COMPARATOR GENERAL DESCRIPTION: THE GFC2100A IS A MAGNITUDE COMPARATOR. IT COMPARES TWO 16-BIT BINARY NUMBERS AND YIELDS THREE OUTPUTS A>B, A<B, AND A-B . PIN DIAGRAM: GFC2100A - GATES USED - 170 •AREA USED - 183 GATE

zn21

Abstract: Transistor R25 r23 transistor zn15 ZN27 R26 transistor R13/r25 transistor
Contextual Info: GFC1020A GFC1020A GFC1020A 32-BIT BARREL SHIFTER GENERAL DESCRIPTION: THE GFC1020A MEGAFUNCTION PERFORMS A 32-BIT END—AROUND SHIFT, OR BARREL SHIFT. THERE ARE FIVE CONTROL LINES SI, S2 , S4 , S8, AND S16 TO DETERMINE HOW MANY PLACES TO THE LEFT THE 32-BIT INPUTS (R31 THROUGH RO) WILL BE SHIFTED AT THE

Contextual Info: GFI2590A GFI2590A GFI2590A PROGRAMMABLE INTERRUPT CONTROLLER G E NERAL DESCRIPTION: THE GFI2590A IS A PROGRAMMABLE INTERRUPT CONTROLLER FOR USE IN A MICROCOMPUTER SYSTEM. IT CAN RESOLVE 8 PRIORITY INTERRUPTS TO THE CPU, OR CASCADE UP TO 64 LEVELS TO THE CPU WITHOUT ADDITIONAL CIRCUITRY. ALL THE OPERATION MODE AND

transistor N14

Abstract: n7 transistor transistor n15 n10 transistor N4 transistor P-029 P08 transistor LSA2000 p023 transistor
Contextual Info: GFB2020A GFB2020A GFB2020A 16 X 16 2 'S COMPLIMENT MULTIPLIER GENERAL DESCRIPTION: THE GFB2020A MEGAFUNCTION IS A 16 X 16 2 'S COMPLEMENT MULTIPLIER WHICH GENERATES A 32-BIT PRODUCT. BY USING A MODIFIED BOOTH ALGORITHM, THIS MEGAFUNCTION GIVES A REASONABLE SPEED AND GATE COUNT.

amd 2900

Abstract: LSA200 Am2910 GFA0100A
Contextual Info: GFAOIOOA GFAOIOOA GFAOIOOA MICROPROGRAM CONTROLLER GENERAL DESCRIPTION: THE GFAOIOOA IS A 12-BIT WIDE ADDRESS SEQUENCER WHICH CONTROLS THE SEQUENCE OF EXECUTION OF THE MICRO-INSTRUCTIONS . IT IS DESIGNED TO BE FULLY COMPATIBLE WITH THE AM2910 EXCEPT WHEN ILLEGAL OPERATIONS ARE PERFORMED ON THE STACK E.G. , TRYING

amd 2900

Abstract: AM2910A
Contextual Info: GFA0102A GFA0102A GFA0102A MICROPROGRAM CONTROLLER GENERAL DESCRIPTION: THE GFA0X02A IS A 9-DEEP STACK, 12-BIT WIDE ADDRESS SEQUENCER WHICH CONTROLS THE SEQUENCE OF EXECUTION OF THE MICRO-INSTRUCTIONS. IT IS DESIGNED TO BE FULLY COMPATIBLE WITH THE AM2910A, EXCEPT WHEN ILLEGAL OPERATIONS ARE PERFORMED ON THE

amd 2900

Abstract: AM2911
Contextual Info: G F A O llO A G F A O llO A GFAOllOA 4-BIT MICROPROGRAM SEQUENCER GENERAL DESCRIPTION: THE GFAOllOA IS A 4-BIT HIDE ADDRESS CONTROLLER WHICH ARRANGES IN SEQUENCE A SERIES OP MICRO-INSTRUCTIONS. IT IS DESIGNED TO BE COMPATIBLE WITH THE AM2911 EXCEPT FOR THE ABSENCE OF THE OUTPUT ENABLE CONTROL. THE GFAOllOA IS BASICALLY

4 bit ALU

Contextual Info: GFBIOIOA GFBIOIOA GFBIOIOA 4—BIT ALU GENERAL DESCRIPTION: THE GFBIOIOA MEGAFUNCTION IS LOGICALLY IDENTICAL TO THE FAIRCHILD 100181, EXCEPT FOR THE ABSENCE OF THE OUTPUT LATCHES AND THE LATCH ENABLE INPUT SIGNAL. THE GFBIOIOA ARITHMETIC LOGIC UNIT ALU PERFORMS 4 BINARY, 4BCD, AND 8 LOGIC

16-bit alu

Abstract: functional diagram of ALU 16 BIT ALU by 74181 alu 74181 pin diagram Abb M alu 74181 logic GFT1811A 16 BIT ALU 74181 ALU 4bit arithmetic logic alu 74181 logic diagram
Contextual Info: GFT1811A GFT1811A G F T1811A 16-BIT ALU GENERAL DESCRIPTION: THE GFT1811A MEGAFUNCTION IS LOGICALLY IDENTICAL TO THE TI 74181, EXCEPT IT OPERATES ON TWO 16-BIT BORDS INSTEAD OF TWO 4-BIT WORDS. THE GFT1811A ARITHMETIC LOGIC DNIT ALU PERFORMS 16 LOGICAL AND 16 BINARY ARITHMETIC OPERATIONS ON TWO

transistor z14 L

Abstract: transistor z9 Transistor Z14
Contextual Info: GFCIOIOA GFCIOIOA G F CIOIOA 16-BIT BARREL SHIFTER GENERAL DESCRIPTION: THE GFCIOIOA MEGAFUNCTION PERFORMS » 16-BIT END-AROUND SHIFT, OR A BARREL SHIFT. THERE ARE FOUR CONTROL LINES SI, S2 , S4, AND SB TO DETERMINE HOW MANY PLACES TO THE LEFT THE 16-BIT INPOTS (R15 THROUGH RO) WILL BE SHIFTED AT THE OUTPUTS