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    GS8662S36E-167

    Abstract: GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333 24 c 1024 w
    Text: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36E-333/300/250/200/167 165-Bump GS8662S08GE-167I GS866x36E-300T. 8662Sxx GS8662S36E-167 GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333 24 c 1024 w

    Untitled

    Abstract: No abstract text available
    Text: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, AN1021

    GS818

    Abstract: No abstract text available
    Text: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36E-333/300/250/200/167 165-Bump 165-bump, 144Mb 165-Pin GS866x36E-300T. GS818

    AN1021

    Abstract: No abstract text available
    Text: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaSIO Interface


    Original     		PDF GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump AN1021

    Untitled

    Abstract: No abstract text available
    Text: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, SR/37 8662Sxx

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, 8662Sxx

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, 8662Sxx

    GS8662S18E-167I

    Abstract: GS8662S36E-167 GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333
    Text: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36E-333/300/250/200/167 165-Bump 8662Sxx GS8662S18E-167I GS8662S36E-167 GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36E-333/300/250/200/167 165-Bump 144Mb 165-bump, pack167 GS866x36E-300T. 8662Sxx

    Untitled

    Abstract: No abstract text available
    Text: GS8662S08/09/18/36E-250/200/167 250 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 SigmaSIO DDR-II SRAM 165-Bump BGA Commercial Temp Industrial Temp A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K.


    Original     		PDF GS8662S08/09/18/36E-250/200/167 165-Bump 144Mb 165-bump,

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36E-333/300/250/200/167 165-Bump 144Mb 165-bump, 8662Sxx

    Untitled

    Abstract: No abstract text available
    Text: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaSIO Interface


    Original     		PDF GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump AN1021

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8662S08/09/18/36BD-333/300/250/200/167 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36BD-333/300/250/200/167 165-Bump 165-bump, GS8662S36BD-300T. 8662Sxx

    Untitled

    Abstract: No abstract text available
    Text: GS8662S08/09/18/36BD-400/350/333/300/250 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaSIO Interface


    Original     		PDF GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, SR50/333/300/250 AN1021

    Untitled

    Abstract: No abstract text available
    Text: GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 SigmaSIO DDR-II SRAM 165-Bump BGA Commercial Temp Industrial Temp A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K.


    Original     		PDF GS8662S08/09/18/36E-333/300/250/200/167 165-Bump 144Mb 165-bump,

    AN1021

    Abstract: GS8662S36E-167 GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333
    Text: GS8662S08/09/18/36E-333/300/250/200/167 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 SigmaSIO DDR-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO™ DDR-II Interface • JEDEC-standard pinout and package


    Original     		PDF GS8662S08/09/18/36E-333/300/250/200/167 165-Bump 8662Sxx AN1021 GS8662S36E-167 GS8662S36E-200 GS8662S36E-250 GS8662S36E-300 GS8662S36E-333