7C3383A Search Results

CY7C383A

Contextual Info: 7C3383A CY7C3384A W0 C Y P R E S S Features • Very high speed — Loadable counter frequencies greater than 80 MHz — Chip-lo-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithm etic, and random logic

CY7C3383A-0JC

Abstract: CY7C3383A-1JC CY7C3383A-1JI
Contextual Info: 7C3383A: January 4, 1995 Revision: October 9, 1995 7C3383A CY7C3384A UltraLogict 3.3V High Speed 2K Gate CMOS FPGA Features D Very high speed D D D D D D Functional Description Ċ See Development Systems section D 5V tolerant Inputs see IIH spec D Robust routing resources

CY7C3382A

Abstract: CY7C3383A CY7C3384A CY7C3385A
Contextual Info: 7C3383A CY7C3384A y CYPRESS Features • Very high speed — Loadable counter frequencies greater than 80 MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic

programmer manual EPLD cypress

Abstract: pASIC380 programming manual EPLD CY7C383A GAL programmer schematic
Contextual Info: filename: Tuesday, August 11, 1992 Revision: October 9, 1995 pASIC380 Family UltraLogict Very High Speed CMOS FPGAs D Robust routing resources Features D Very high speed D D D D D D D Ċ Loadable counter frequencies greater than 150 MHz Ċ ChipĆtoĆchip operating frequencies

Contextual Info: 7C3383A CY7C3384A y CYPRESS Features • Very high speed — Loadable counter frequencies greater than 80 MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic

Contextual Info: > CYPRESS Features • Full 33V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-8-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,