74LS12P Search Results
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M74LS12P
Abstract: 74LS12P 20-PIN
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M74LS12P M74LS12P 500ns, 50ffc. b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS12P | |
74LS12PContextual Info: MITSUBISHI LSTTLs M 7 4 LS1 2 P T R IP L E 3-INPUT P O SITIV E NAND GATE WITH OPEN CO LLECTO R OUTPUT DESCRIPTION The 74LS12P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing three triple-input positive-logic NAND gates with open collector outputs, usable as negative-logic NOR |
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M74LS12P 50ffc. b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS12P | |
transistor cross reference
Abstract: MPT3N40 Westinghouse SCR handbook LT 8224 ZENER DIODE sje389 N9602N npn transistor RCA 467 TFK 7 segment displays PUT 2N6027 delco 466
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transistor C3866
Abstract: Zener PH SEC E13009 ups circuit schematic diagram 1000w E13007 2 E13007 C3866 power transistor texas ttl 74L505 Transistor C3246
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