Untitled
Abstract: No abstract text available
Text: GD54/74HC32, GD54/74HCT32 QUAD 2-INPUT OR GATES General Description These devices are identical in pinout to the 54/74LS 32. They contain four independent 2-input OR gates. These devices are characterized for operation over wide temperature ranges to meet in
|
OCR Scan
|
GD54/74HC32,
GD54/74HCT32
54/74LS
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GD54/74HC86, GD54/74HCT86 QUAD 2- INPUT EXCLUSIVE OR GATES General Description These devices are identical in pinout to the 54/74LS 86. They contain four independent 2-input Exclusive OR gates. These devices are characteriz ed for operation over wide temperature ranges to
|
OCR Scan
|
GD54/74HC86,
GD54/74HCT86
54/74LS
|
PDF
|
74LS58
Abstract: 74HCT58 GD74HC58 54/74LS58 74HC GD54HC58
Text: GD54/74HC58, GD54/74HCT58 DUAL AND-OR GATES General Description These devices are identical in pinout to the 54/74LS 58. They contain one 2-wide 2-input & one 2-wide 3-input AND-OR gates. These devices are characterized for operation over wide temperature ranges to meet industry and military
|
OCR Scan
|
GD54/74HC58,
GD54/74HCT58
54/74LS58.
GD74HCT58
GD54HCT58
74LS58
74HCT58
GD74HC58
54/74LS58
74HC
GD54HC58
|
PDF
|
Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series D N 74LS 136 DN74LS136 ro 7q. LS 2>£> Quad 2 - input E xclusive OR G ates with Open C ollector Outputs) • Description P-1 DN74LS136 contains four 2-input exclusive OR gate circuits w ith open collector o utputs. ■ Features • •
|
OCR Scan
|
DN74LS
DN74LS136
DN74LS136
14-pin
SO-14D)
S15ns,
|
PDF
|
Zytrex OR gate
Abstract: 74HCTLS
Text: Z v t r e ZX54HCTLS ZX74HCTLS x Quad 2-Input Exclusive-OR Gates February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input Exclu
|
OCR Scan
|
54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
Zytrex OR gate
74HCTLS
|
PDF
|
74hctls
Abstract: Zytrex OR gate
Text: Z v t r e ZXS4HCTLS ZX74HCTLS x _ K A Quad 2-Input OR Gates February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, ptn-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input OR gates. They perform the Boolean functions Y = A + B
|
OCR Scan
|
54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
74hctls
Zytrex OR gate
|
PDF
|
74L86
Abstract: No abstract text available
Text: SN54LS386A, SN74LS386A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES MARCH 1974 - REVISED MARCH 198B SN 54LS 386A . . . J OR W PACKAGE SN 74LS 386A . . . D OR N PACKAGE Electrically Identical to SN54LS86A/SN74LS86A TOP VIEW Mechanically Identical to SN 54L86/S N 74L86
|
OCR Scan
|
SN54LS386A,
SN74LS386A
SN54LS86A/SN74LS86A
54L86/S
74L86
|
PDF
|
74hctls
Abstract: No abstract text available
Text: Zytrex_ æ&OO Quad 2-Input NAND Gates February 1965 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input NAND gatesJhat perform the Boolean functions Y = A • B or
|
OCR Scan
|
54/74LS
74HCTLS:
54HCTLS:
ZX74HCTLS
74hctls
|
PDF
|
M74LS32P
Abstract: 20-PIN 3B03
Text: MITSUBISHI LSTTLs M74LS32P QUADRUPLE 2 -IN P U T P O S IT IV E OR GATES DESCRIPTION The M 74LS 32P is a semiconductor integrated circuit containing 4 dual-input positive OR and negative A N D gates. FEATURES • High breakdown input voltage V | S 15 V •
|
OCR Scan
|
M74LS32P
M74LS32P
16-PIN
20-PIN
3B03
|
PDF
|
Zytrex quad and gate
Abstract: 74hctls
Text: Z y tr c x _ February1985 08 Quad 2-Input AND Gâté# / OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input AND gates. They perform the Boolean functions Y = A • B or
|
OCR Scan
|
ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
Zytrex quad and gate
74hctls
|
PDF
|
74LS32P
Abstract: M74LS32P
Text: MITSUBISHI LSTTLs M74LS32P QUADRUPLE 2 -IN P U T P O S IT IV E OR GATES DESCRIPTION The M 74LS 32P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing 4 dual-input positive OR and negative A N D gates. FEATURES • High breakdown input voltage (V | S 15 V )
|
OCR Scan
|
M74LS32P
500ns,
0013Sbl
74LS32P
M74LS32P
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M 74LS136P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATES W ITH OPEN COLLECTOR OUTPUTS DESCRIPTION The M 74LS 136P containing 4 is a semiconductor integrated circuit dual-input exclusive-OR gates w ith PIN CONFIGURATION TOP VIEW open collector output.
|
OCR Scan
|
74LS136P
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
|
PDF
|
M74LS136P
Abstract: 20-PIN MITSUBISHI ELECTRIC SEMICONDUCTOR
Text: MITSUBISHI LSTTLs M 74LS136P QUADRUPLE 2 -IN P U T EXC LU SIVE OR GATES W IT H OPEN COLLECTOR O UTPU TS DESCRIPTION The M 74LS 136P containing 4 is a semiconductor integrated circuit dual-input exclusive-OR gates w ith PIN CONFIGURATION TOP VIEW open collector output.
|
OCR Scan
|
M74LS136P
M74LS136P
16-PIN
20-PIN
MITSUBISHI ELECTRIC SEMICONDUCTOR
|
PDF
|
M74LS09P
Abstract: 20-PIN
Text: MITSUBISHI LSTTLs M74LS09P QUADRUPLE 2-IN P U T POSITIVE AND GATES W ITH OPEN COLLECTOR OUTPUTS DESCRIPTION The M 74LS 09P is a semiconductor integrated circuit containing 4 dual-input positive A N D and negative OR gates w ith open collector output. FEATURES
|
OCR Scan
|
M74LS09P
M74LS09P
16-PIN
20-PIN
|
PDF
|
|
|
D73-Y
Abstract: D73y ic 74145
Text: SAMSUNG SEM IC O N D U C T OR INC 05 DEI 7^4145 . KS54HCTLS O O KS74HCTLS ~ 000^301 S T -4 3 -a i Quad 2-Input OR Gates FEATURES DESCRIPTION • Function, pln-out, speed and drive compatibility with 54/74LS logic family • Low power consumption characteristic of CMOS
|
OCR Scan
|
KS54HCTLS
KS74HCTLS
54/74LS
KS74HCTLS:
KS54HCTLS:
300-mil
7Tb414S
90-XO
14-Pin
D73-Y
D73y
ic 74145
|
PDF
|
hctls86
Abstract: No abstract text available
Text: SAMSUNG SEMICONDUCTOR INC OB DE^ 7 H m M a K S S 4 H C T L S O ^ . KS74HCTLS 000^330 7 '7_" - ^ 3 -v2 Quad 2-Input Exclusive-OR Gates FEATURES DESCRIPTION • Function, pin-out, speed and drive compatibility with 54/74LS logic family
|
OCR Scan
|
KS74HCTLS
54/74LS
KS74HCTLS:
KS54HCTLS:
300-mil
7Tb414S
90-XO
14-Pin
hctls86
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SAMSUNG SE MI C O N D U C T OR INC 02 • KS¿4HCTLS f Í Q *K S 74H C T L S W D E | 7 ^ 4 1 4 2 □00b2afl 1 Quad 2-Input AND Gates with Open-Drain Outputs FEATURES DESCRIPTION • Function, pinout, speed and drive compatibility with 54/74LS logic family
|
OCR Scan
|
00b2afl
54/74LS
KS74HCTLS:
KS54HCTLS:
300-mil
7Tb414S
90-XO
14-Pin
|
PDF
|
ic ttl 7408
Abstract: 74LS08 texas instruments TTL 7408 74s08 7408 IC and TTL SN74LS08
Text: TYPES SN5408, SN54LS08, SN54S08, SN7408, SN74LS08, SN74S08 QUADRUPLE 2-INPUT POSITIVE-AND GATES REVISED DECEMBER 1983 S N 5 4 G 8 , S N 5 4 L S 0 8 , S N 5 4 S 0 8 . . . J OR W P A C K A G E SN 7408 . J OR N PACKAG E S N 74LS 08, S N 7 4 S 0 8 . . . D, J OR N PACKAG E
|
OCR Scan
|
SN5408,
SN54LS08,
SN54S08,
SN7408,
SN74LS08,
SN74S08
SN54S08
ic ttl 7408
74LS08 texas instruments
TTL 7408
74s08
7408 IC and
TTL SN74LS08
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SAMSUNG S E M I CON DU CT OR INC OE KS54HCTLS f ì i KS74HCTLS v 1 F e | T U M l M a 000 bE7L s | ~T-*f3-aj • Quad 2-Input NAND Gates with Open-Drain Outputs FEATURES DESCRIPTION • Function, pin-out, speed and drive compatibility with S4/74LS logic family
|
OCR Scan
|
KS54HCTLS
KS74HCTLS
7Tb414S
90-XO
14-Pin
|
PDF
|
Untitled
Abstract: No abstract text available
Text: H D 74LS 54 •4 -w ¡d e 2-¡nput, 3-input AND-OR-INVERT Gates IP IN ARRANGEMENT IC IR C U IT SCHEM ATIC N o te The schem atic w ith in th e dashed lin e is in clu de d th e h a lf in p u t te rm in a ls o f H D 7 4 L S 5 4 . •ELECTRICAL CHARACTERISTICS Ta= - 2 0 - +75°C )
|
OCR Scan
|
400//A
T-90-10
74LSOO
ib203
|
PDF
|
74ls Logic Family Specifications
Abstract: 74LS 74LS136 74Ls signetics 74LS 3 input AND gate
Text: 74LS136 Signetics Gate Quad Two-Input Exclusive-OR Gate Open Collector Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 18ns 6.1mA 74LS136 ORDERING CODE FUNCTION TABLE INPUTS OUTPUT A B Y L L H H L H L H
|
OCR Scan
|
74LS136
N74LS136N
10LSul
20/jtA
WF07570S
F07380S
74ls Logic Family Specifications
74LS
74LS136
74Ls signetics
74LS 3 input AND gate
|
PDF
|
74LS266 pin configuration
Abstract: TTL 74LS266 74ls Logic Family Specifications 74LS 74Ls signetics
Text: 74LS266 Signetics Gate Quad 2-Input Exclusive-NOR Gate Open Collector Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 18ns 8mA 74LS266 FUNCTION TABLE INPUTS ORDERING CODE OUTPUT A B Y L L H H L H L H H L
|
OCR Scan
|
74LS266
N74LS266N
10LSul
500ns
500ns
74LS266 pin configuration
TTL 74LS266
74ls Logic Family Specifications
74LS
74Ls signetics
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Signetics 74LS266 Gate Quad 2-Input Exclusive-NOR Gate Open Collector Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 18ns 8mA 74LS266 FUNCTION TABLE INPUTS ORDERING CODE OUTPUT A B Y L L H H L H L H H L
|
OCR Scan
|
74LS266
74LS266
N74LS266N
10LSul
20/iA
500ns
500ns
|
PDF
|
TTL 74ls54
Abstract: 74ls Logic Family Specifications 74LS54 74LS
Text: 74LS54 Gate S ignetics Four-Wide Two- & Three-Input AND-OR-lnvert Gate Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 12ns 0.9mA 74LS54 ORDERING CODE COMMERCIAL RANGE VCC = 5 V ± 5 % ; T A = 0°C to +70°C
|
OCR Scan
|
74LS54
74LS54
N74LS54N
N74LS54D
F07S70S
TTL 74ls54
74ls Logic Family Specifications
74LS
|
PDF
|
