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Texas Instruments 74AC11032DBR Logic Gates Quad 2-Input
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Mouser Electronics	74AC11032DBR					1 $2.42 10 $2.42 100 $2.23 1000 $1.91 10000 $1.36	Get Quote

74AC11032DBRG4 Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
74AC11032DBRG4		Texas Instruments	Quadruple 2-Input Positive-OR Gates 16-SSOP -40 to 85		Original	PDF
74AC11032DBRG4		Texas Instruments	74AC11032 - Quadruple 2-Input Positive-OR Gates 16-SSOP -40 to 85		Original	PDF

74AC11032DBRG4 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil	PDF
Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil	PDF
Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil MSSO002E MO-150	PDF
Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil MSSO002E MO-150	PDF
Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil MSSO002E MO-150	PDF
Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil	PDF
74AC11032 Abstract: 74AC11032D 74AC11032DBLE 74AC11032DBR 74AC11032DBRE4 74AC11032DBRG4 74AC11032DE4 74AC11032DG4 74AC11032DR Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil 74AC11032 74AC11032D 74AC11032DBLE 74AC11032DBR 74AC11032DBRE4 74AC11032DBRG4 74AC11032DE4 74AC11032DG4 74AC11032DR	PDF
Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil MSSO002E MO-150	PDF
74AC11032 Abstract: 74AC11032D 74AC11032DBLE 74AC11032DBR 74AC11032DBRE4 74AC11032DBRG4 74AC11032DE4 74AC11032DG4 74AC11032DR Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil MO-150 74AC11032 74AC11032D 74AC11032DBLE 74AC11032DBR 74AC11032DBRE4 74AC11032DBRG4 74AC11032DE4 74AC11032DG4 74AC11032DR	PDF
Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process	Original	74AC11032 SCAS007C 500-mA 300-mil	PDF