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    74AC10 Search Results

    74AC10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CD74AC10M Texas Instruments Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    SN74AC10DR Texas Instruments Triple 3-Input Positive-NAND Gates 14-SOIC -40 to 85 Visit Texas Instruments Buy
    CD74AC10M96 Texas Instruments Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74AC109E Texas Instruments Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 Visit Texas Instruments Buy
    CD74AC10E Texas Instruments Triple 3-Input NAND Gates 14-PDIP -55 to 125 Visit Texas Instruments Buy
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    74AC10 Price and Stock

    Texas Instruments SN74AC10DR

    IC GATE NAND 3CH 3-INP 14SOIC
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    DigiKey SN74AC10DR Cut Tape 7,079 1
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    onsemi MC74AC10DR2G

    IC GATE NAND 3CH 3-INP 14SOIC
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    DigiKey MC74AC10DR2G Digi-Reel 4,990 1
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    Bristol Electronics MC74AC10DR2G 1,529
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    Texas Instruments SN74AC10PWR

    IC GATE NAND 3CH 3-INP 14TSSOP
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    DigiKey SN74AC10PWR Digi-Reel 3,990 1
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    Mouser Electronics SN74AC10PWR 1,923
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    Rochester Electronics SN74AC10PWR 17,260 1
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    Texas Instruments CD74AC10M96

    IC GATE NAND 3CH 3-INP 14SOIC
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    DigiKey CD74AC10M96 Cut Tape 2,466 1
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    CD74AC10M96 Digi-Reel 2,466 1
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    Mouser Electronics CD74AC10M96 2,445
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    Rochester Electronics CD74AC10M96 23,355 1
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    Ameya Holding Limited CD74AC10M96 2,507
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    Texas Instruments SN74AC10DBR

    IC GATE NAND 3CH 3-INP 14SSOP
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    DigiKey SN74AC10DBR Digi-Reel 2,000 1
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    Rochester Electronics SN74AC10DBR 16,000 1
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    74AC10 Datasheets (90)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AC10 Fairchild Semiconductor Triple 3-Input NAND Gate Original PDF
    74AC10 STMicroelectronics Triple 3-Input NAND Gate Original PDF
    74AC10 STMicroelectronics TRIPLE 3-INPUT NAND GATE Original PDF
    74AC10 STMicroelectronics TRIPLE 3-INPUT NAND GATE Original PDF
    74AC1010-55DC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74AC1010-55PC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74AC1010-55QC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74AC1010-65DC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74AC1010-65PC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74AC1010-65QC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74AC1016-55 Fairchild Semiconductor 16 x 16 Parallel Multiplier Scan PDF
    74AC1016-65 Fairchild Semiconductor 16 x 16 Parallel Multiplier Scan PDF
    74AC109 Fairchild Semiconductor Dual JK Positive Edge-Triggered Flip-Flop Original PDF
    74AC109 Fairchild Semiconductor Dual JK Positive Edge-Triggered Flip-Flop Original PDF
    74AC109 Fairchild Semiconductor Dual JK Positive Edge-Triggered Flip-Flop Original PDF
    74AC109 Fairchild Semiconductor Dual JK Positive Edge-Triggered Flip- Original PDF
    74AC109 Texas Instruments Dual J-K Flip-Flop with Set and Reset Original PDF
    74AC109CW Fairchild Semiconductor Dual JK Positive Edge-Triggered Flip-Flop Original PDF
    74AC109DC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74AC109DCQR National Semiconductor Dual JK Positive Edge-Triggered Flip-Flop Original PDF

    74AC10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74AC109

    Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC
    Text: Revised November 1999 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock


    Original     		PDF 74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC

    74AC109MTC

    Abstract: 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109SC
    Text: Revised August 2000 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock


    Original     		PDF 74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109MTC 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109SC

    74AC109

    Abstract: 74AC109MTC 74ACT109 74AC109SC 74AC109SJ 74ACT109PC 74ACT109SC
    Text: 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop tm Features General Description • ICC reduced by 50% The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the


    Original     		PDF 74AC109, 74ACT109 AC/ACT109 AC/ACT74 ACT109 74ACT109 74AC109 74AC109MTC 74AC109SC 74AC109SJ 74ACT109PC 74ACT109SC

    74AC10

    Abstract: 74AC 74AC10MTC 74AC10PC 74AC10SC 74AC10SJ 74ACT10 74ACT10PC 74ACT10SC
    Text: Revised February 2005 74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The AC/ACT10 contains three, 3-input NAND gates. • ICC reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number 74AC10SC


    Original     		PDF 74AC10 74ACT10 AC/ACT10 74AC10SC 74AC10SJ 74AC10MTC MTC14 14-Lead MS-012, 74AC10 74AC 74AC10MTC 74AC10PC 74AC10SC 74AC10SJ 74ACT10 74ACT10PC 74ACT10SC

    sop65p640

    Abstract: SOP65
    Text: 74AC10, 74ACT10 Triple 3-Input NAND Gate Features General Description • ICC reduced by 50% on 74AC only The AC/ACT10 contains three, 3-input NAND gates. ■ Outputs source/sink 24mA Ordering Information Order Number Package Number 74AC10SC 74AC10SJ 74AC10MTC


    Original     		PDF 74AC10, 74ACT10 AC/ACT10 74AC10SC 74AC10SJ 74AC10MTC MTC14 14-Lead MS-012, sop65p640 SOP65

    74AC

    Abstract: 74AC10 74AC10MTC 74AC10PC 74AC10SC 74AC10SJ 74ACT10 74ACT10PC 74ACT10SC
    Text: Revised January 2000 74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The AC/ACT10 contains three, 3-input NAND gates. • ICC reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description


    Original     		PDF 74AC10 74ACT10 AC/ACT10 14-Lead MS-120, 74AC10SC 74AC10SJ 74AC10MTC MTC14 74AC 74AC10 74AC10MTC 74AC10PC 74AC10SC 74AC10SJ 74ACT10 74ACT10PC 74ACT10SC

    74AC109SC

    Abstract: 74AC109 74AC109PC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC
    Text: Revised October 1998 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to CD Clear sets Q to LOW level The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking


    Original     		PDF 74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109SC 74AC109 74AC109PC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC

    74AC390

    Abstract: 74AC54D 74ac841 74AC163 74AC393 74AC245 74AC670 74ac109 74AC623 74ACT640
    Text: SELECTION GUIDE TC74AC/ACT Series Selection Guide NAND 74AC00 74ACTOO NOR 74AC02 74ACT02 AND 74AC08 74ACT08 OR 74AC32 74ACT32 INVERTER, BUFFER 74AC04 74ACT04 EXCLUSIVE OR 74AC86 74ACT86 GATE SCHMITT TRIGGER BUS BUFFER BUFFER BUS TRANSCEIVER 74AC10 74ACT10


    OCR Scan     		PDF TC74AC/ACT 74AC00 74AC02 74AC08 74AC32 74AC04 74AC86 74AC14 74AC125 74AC244 74AC390 74AC54D 74ac841 74AC163 74AC393 74AC245 74AC670 74ac109 74AC623 74ACT640

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Tf x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC H S282 IS- » 2 1JÎK IC f*ÎR • 3 4 1 1 • IO Dual “J-K” Flip-Flop with Set and Reset F /F 1 CD54/74AC/ACT109 - Positive-Edge-Triggered J, K


    OCR Scan     		PDF CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CS-36532 CD54/74AC109

    S35R2

    Abstract: 1278n 74aC-aCT109 CD541 j8332 RCA
    Text: HARRIS SEMICOND SECTOR 37E D • 4302271 D025411 6 *HAS _ Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information 07 Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K


    OCR Scan     		PDF 43G5571 CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 -ik-07- 92CS-J8332 CD54/74AC/ACT109 CD54/74AC/ACT112 S35R2 1278n 74aC-aCT109 CD541 j8332 RCA

    74AC109

    Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 M16A M16D
    Text: S H IU D Revised O ctober 1998 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LO W input to Cp Clear sets Q to LOW level T h e AC /AC T109 consists of two_ high-speed com pletely independent transition clocked JK flip-flops. The clocking


    OCR Scan     		PDF 74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 M16A M16D

    Untitled

    Abstract: No abstract text available
    Text: 43G2271 D G 2 S 4 H 37E D HARRIS SEMICOND SECTOR _ ñ *HAS Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information T^fc-or?- 0 7 Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K


    OCR Scan     		PDF 43G2271 CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CD54/74AC/ACT109 54/74AC109 CD54/74AC

    Untitled

    Abstract: No abstract text available
    Text: 53 National ÆM Semiconductor 54AC/74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The 'AC/'ACTIO contains three, 3-input NAND gates. • Icc reduced by 50% on 54AC/74AC only ■ Outputs source/sink 24 mA ■ Standard Military Drawing SMD


    OCR Scan     		PDF 54AC/74AC10 74ACT10 54AC/74AC 54ACT10 54ACTQ10 74ACT

    Untitled

    Abstract: No abstract text available
    Text: AC1017 • ACT1017 54AC/74AC1017 • 54ACT/74ACT1017 16 x 16 Parallel Multiplier Description Connection Diagram The 'AC/’ACT1017 is a high-speed, low power 16 x 16-bit parallel multiplier that is ideally suited for real-time digital signal processing applications.


    OCR Scan     		PDF AC1017 ACT1017 54AC/74AC1017 54ACT/74ACT1017 16-bit Am29517

    Untitled

    Abstract: No abstract text available
    Text: AC109 • ACT109 54AC/74AC109 • 54ACT/74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flipflops. The clocking operation is independent of


    OCR Scan     		PDF AC109 ACT109 54AC/74AC109 54ACT/74ACT109 ACT109 ACT74 54/74A

    615162

    Abstract: No abstract text available
    Text: NATIONAL SEMICOND L06IC blE b 5 D 1 1 2 2 00747flb bTb « N S C 1 J> T - H L 'O T - 0 7 03 National ÆM Semiconductor 54AC/74AC109 • 54ACT/74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’AC /’ACT109 consists of two high-speed completely


    OCR Scan     		PDF L06IC) 00747flb 54AC/74AC109 54ACT/74ACT109 ACT109 ACT74 74ACT 54ACT 125-C 615162

    Untitled

    Abstract: No abstract text available
    Text: Technical Data „ , CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features:


    OCR Scan     		PDF CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CD54/74AC109 CD54/74ACT109

    Untitled

    Abstract: No abstract text available
    Text: Technical Data , CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Informaron Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features: • Buffered inputs


    OCR Scan     		PDF CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CD54/74AC/ACT CD54/74AC109 CD54/74ACT109

    ZD302

    Abstract: No abstract text available
    Text: 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to C q Clear sets Q to LOW level T h e AC /AC T109 consists of two_ high-speed com pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall tim es of th e clock


    OCR Scan     		PDF 74AC109 74ACT109 ZD302

    Untitled

    Abstract: No abstract text available
    Text: HA RR IS S E H I C O N D S E C T O R 37E D m 4 3 0 2 E7 1 D0S53flS S Technical Data ^ CD54/74AC10 C D 54/74A C T10 G E SOLID STATE Advance Information Triple 3-Input NAND Gate Type Features: • Typical propagation delay AC10 : 6 n s @ V cc = 5 V. Ta = 25° C, C l = 50 p F


    OCR Scan     		PDF D0S53flS CD54/74AC10 54/74A CD54/74ACT10 CD74AC10 CD74ACT10 14-lead MS-013AD)

    Untitled

    Abstract: No abstract text available
    Text: AC10 54AC/74AC10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA Ordering Code: See Section 6 Pin Assignment for LCC Pin Assignment for DIP, Flatpak and SOIC DC Characteristics unless otherwise specified Parameter Symbol Icc Maximum Quiescent Supply Current


    OCR Scan     		PDF 54AC/74AC10 54/74AC

    Untitled

    Abstract: No abstract text available
    Text: March 1993 Semiconductor 54AC/74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The ’AC /’ACT10 contains three, 3-input NAND gates. • Ice reduced by 50% on 54AC/74AC only ■ Outputs source/sink 24 mA ■ Standard Military Drawing SMD


    OCR Scan     		PDF 54AC/74AC10 74ACT10 ACT10 54AC/74AC 54ACT10 54ACTQ10 75/Printed 20-3A

    Untitled

    Abstract: No abstract text available
    Text: Revised October 1998 j,f > i '' ^ : 3? •? » 74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The AC/ACT10 contains three, 3-input NAND gates. ■ lc c reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Order Number


    OCR Scan     		PDF 74AC10 74ACT10 AC/ACT10 14-Lead MS-120, 74AC1OSC 74AC1OSJ 74AC1OMTC MTC14

    Untitled

    Abstract: No abstract text available
    Text: AC10 54AC/74AC10 Triple 3-Input NAND Gate Connection Diagrams 1Outputs Source/Sink 24 mA a 0s a e Ordering Code: See Section 6 Pin Assignment for LCC Pin Assignment for DIP, Flatpak and SOIC DC Characteristics unless otherwise specified Symbol Parameter


    OCR Scan     		PDF 54AC/74AC10 54/74AC