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    74ACT10 Search Results

    74ACT10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CD74ACT109ME4 Texas Instruments Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 Visit Texas Instruments Buy
    SN74ACT10D Texas Instruments Triple 3-Input Positive-NAND Gates 14-SOIC -40 to 85 Visit Texas Instruments Buy
    SN74ACT10N Texas Instruments Triple 3-Input Positive-NAND Gates 14-PDIP -40 to 85 Visit Texas Instruments Buy
    SN74ACT1073DW Texas Instruments 16-Bit Bus Termination Networks With Bus Hold Function 20-SOIC -40 to 85 Visit Texas Instruments Buy
    SN74ACT10DBR Texas Instruments Triple 3-Input Positive-NAND Gates 14-SSOP -40 to 85 Visit Texas Instruments Buy
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    74ACT10 Price and Stock

    Rochester Electronics LLC MC74ACT109DR2

    IC FF JK TYPE DUAL 1BIT 16SOP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey MC74ACT109DR2 Bulk 116,450 3,806
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    Rochester Electronics LLC SN74ACT1073DWR

    SN74ACT1073 16-BIT BUS TERMINATI
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74ACT1073DWR Bulk 25,825 152
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    Rochester Electronics LLC SN74ACT10DBR

    IC GATE NAND 3CH 3-INP 14SSOP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74ACT10DBR Bulk 25,750 1,055
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    Rochester Electronics LLC MC74ACT10NG

    IC GATE NAND 3CH 3-INP 14DIP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey MC74ACT10NG Tube 25,284 1,158
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    Rochester Electronics LLC SN74ACT10D

    IC GATE NAND 3CH 3-INP 14SOIC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74ACT10D Bulk 15,631 507
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    Find more 74ACT10 price and stock on Findchips.com

    74ACT10 Datasheets (66)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74ACT10 Fairchild Semiconductor Triple 3-Input NAND Gate Original PDF
    74ACT10 Fairchild Semiconductor Triple 3-Input NAND Gate Original PDF
    74ACT10 STMicroelectronics Triple 3-Input NAND Gate Original PDF
    74ACT1010-55DC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74ACT1010-55PC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74ACT1010-55QC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74ACT1010-65DC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74ACT1010-65PC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74ACT1010-65QC RCA Solid State 16 x 16 Parallel Multiplier/Accumulator Scan PDF
    74ACT1016 National Semiconductor 16 x 16 Parallel Multiplier Scan PDF
    74ACT1016-55 Fairchild Semiconductor 16 x 16 Parallel Multiplier Scan PDF
    74ACT1016-55PC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74ACT1016-65 Fairchild Semiconductor 16 x 16 Parallel Multiplier Scan PDF
    74ACT1016-65PC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74ACT109 Fairchild Semiconductor Dual JK Positive Edge-Triggered Flip-Flop Original PDF
    74ACT109 Fairchild Semiconductor Dual JK Positive Edge-Triggered Flip- Original PDF
    74ACT109 Texas Instruments Dual J-K Flip-Flop with Set and Reset Original PDF
    74ACT109CW Fairchild Semiconductor Dual JK Positive Edge-Triggered Flip-Flop Original PDF
    74ACT109DC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74ACT109DCQR National Semiconductor Dual JK Positive Edge-Triggered Flip-Flop Original PDF

    74ACT10 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    74AC390

    Abstract: 74AC54D 74ac841 74AC163 74AC393 74AC245 74AC670 74ac109 74AC623 74ACT640
    Text: SELECTION GUIDE TC74AC/ACT Series Selection Guide NAND 74AC00 74ACTOO NOR 74AC02 74ACT02 AND 74AC08 74ACT08 OR 74AC32 74ACT32 INVERTER, BUFFER 74AC04 74ACT04 EXCLUSIVE OR 74AC86 74ACT86 GATE SCHMITT TRIGGER BUS BUFFER BUFFER BUS TRANSCEIVER 74AC10 74ACT10


    OCR Scan     		TC74AC/ACT 74AC00 74AC02 74AC08 74AC32 74AC04 74AC86 74AC14 74AC125 74AC244 74AC390 74AC54D 74ac841 74AC163 74AC393 74AC245 74AC670 74ac109 74AC623 74ACT640 PDF

    master slave jk flip flop

    Abstract: ECL D flip flop Flip Flop DIP Flip flop JK cmos 74lvt16374 d flip flop d type flip flop flip flop flip flop circuit flip flop circuit type D
    Text: Logic Products by Function Flip-Flop Products Logic Product Family Product Description Package Voltage Node 74ACT109 FACT ACT Dual JK Positive Edge-Triggered Flip-Flop DIP SOIC TSSOP 5 DM74LS73A Bipolar-LS Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary


    Original     		74ACT109 DM74LS73A MM74C73 74AC74 74ACT74 74ACTQ74 16-Bit 74VCXH162374 SCAN182374A master slave jk flip flop ECL D flip flop Flip Flop DIP Flip flop JK cmos 74lvt16374 d flip flop d type flip flop flip flop flip flop circuit flip flop circuit type D PDF

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Tf x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC H S282 IS- » 2 1JÎK IC f*ÎR • 3 4 1 1 • IO Dual “J-K” Flip-Flop with Set and Reset F /F 1 CD54/74AC/ACT109 - Positive-Edge-Triggered J, K


    OCR Scan     		CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CS-36532 CD54/74AC109 PDF

    Untitled

    Abstract: No abstract text available
    Text: SGS-THOMSON 74ACT10 M 0 gl3 l[LI(3ra [S!]D(BS TRIPLE 3-INPUT NAND GATE PRELIM IN ARY DATA . HIGH SPEED: tPD = 6.5 ns (TYP. at Vcc = 5V . LOW POWER DISSIPATION: Ice = 4 |xA (MAX.) at TA = 25 °C . COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), V il = 0.8V (MAX)


    OCR Scan     		74ACT10 ACT10 ideaSO-14 P013G PDF

    74AC109

    Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC
    Text: Revised November 1999 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock


    Original     		74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC PDF

    S35R2

    Abstract: 1278n 74aC-aCT109 CD541 j8332 RCA
    Text: HARRIS SEMICOND SECTOR 37E D • 4302271 D025411 6 *HAS _ Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information 07 Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K


    OCR Scan     		43G5571 CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 -ik-07- 92CS-J8332 CD54/74AC/ACT109 CD54/74AC/ACT112 S35R2 1278n 74aC-aCT109 CD541 j8332 RCA PDF

    74AC109

    Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 M16A M16D
    Text: S H IU D Revised O ctober 1998 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LO W input to Cp Clear sets Q to LOW level T h e AC /AC T109 consists of two_ high-speed com pletely independent transition clocked JK flip-flops. The clocking


    OCR Scan     		74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 M16A M16D PDF

    Untitled

    Abstract: No abstract text available
    Text: 43G2271 D G 2 S 4 H 37E D HARRIS SEMICOND SECTOR _ ñ *HAS Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information T^fc-or?- 0 7 Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K


    OCR Scan     		43G2271 CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CD54/74AC/ACT109 54/74AC109 CD54/74AC PDF

    Untitled

    Abstract: No abstract text available
    Text: 53 National ÆM Semiconductor 54AC/74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The 'AC/'ACTIO contains three, 3-input NAND gates. • Icc reduced by 50% on 54AC/74AC only ■ Outputs source/sink 24 mA ■ Standard Military Drawing SMD


    OCR Scan     		54AC/74AC10 74ACT10 54AC/74AC 54ACT10 54ACTQ10 74ACT PDF

    948F

    Abstract: MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N
    Text: MC74AC109, 74ACT109 Dual JK Positive Edge−Triggered Flip−Flop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.


    Original     		MC74AC109, MC74ACT109 MC74AC109/74ACT109 MC74AC74/74ACT74 ACT109 DIP-16 MC74AC109/D 948F MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N PDF

    Untitled

    Abstract: No abstract text available
    Text: AC1017 • ACT1017 54AC/74AC1017 • 54ACT/74ACT1017 16 x 16 Parallel Multiplier Description Connection Diagram The 'AC/’ACT1017 is a high-speed, low power 16 x 16-bit parallel multiplier that is ideally suited for real-time digital signal processing applications.


    OCR Scan     		AC1017 ACT1017 54AC/74AC1017 54ACT/74ACT1017 16-bit Am29517 PDF

    Untitled

    Abstract: No abstract text available
    Text: s e m ic o n d u c t o r Revised November 1999 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two_ high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock


    OCR Scan     		74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 PDF

    Untitled

    Abstract: No abstract text available
    Text: AC109 • ACT109 54AC/74AC109 • 54ACT/74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flipflops. The clocking operation is independent of


    OCR Scan     		AC109 ACT109 54AC/74AC109 54ACT/74ACT109 ACT109 ACT74 54/74A PDF

    615162

    Abstract: No abstract text available
    Text: NATIONAL SEMICOND L06IC blE b 5 D 1 1 2 2 00747flb bTb « N S C 1 J> T - H L 'O T - 0 7 03 National ÆM Semiconductor 54AC/74AC109 • 54ACT/74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’AC /’ACT109 consists of two high-speed completely


    OCR Scan     		L06IC) 00747flb 54AC/74AC109 54ACT/74ACT109 ACT109 ACT74 74ACT 54ACT 125-C 615162 PDF

    74AC109

    Abstract: 74AC109MTC 74ACT109 74AC109SC 74AC109SJ 74ACT109PC 74ACT109SC
    Text: 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop tm Features General Description • ICC reduced by 50% The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the


    Original     		74AC109, 74ACT109 AC/ACT109 AC/ACT74 ACT109 74ACT109 74AC109 74AC109MTC 74AC109SC 74AC109SJ 74ACT109PC 74ACT109SC PDF

    74AC10

    Abstract: 74AC 74AC10MTC 74AC10PC 74AC10SC 74AC10SJ 74ACT10 74ACT10PC 74ACT10SC
    Text: Revised February 2005 74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The AC/ACT10 contains three, 3-input NAND gates. • ICC reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number 74AC10SC


    Original     		74AC10 74ACT10 AC/ACT10 74AC10SC 74AC10SJ 74AC10MTC MTC14 14-Lead MS-012, 74AC10 74AC 74AC10MTC 74AC10PC 74AC10SC 74AC10SJ 74ACT10 74ACT10PC 74ACT10SC PDF

    Untitled

    Abstract: No abstract text available
    Text: Technical Data „ , CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features:


    OCR Scan     		CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CD54/74AC109 CD54/74ACT109 PDF

    Untitled

    Abstract: No abstract text available
    Text: Technical Data , CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Informaron Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features: • Buffered inputs


    OCR Scan     		CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CD54/74AC/ACT CD54/74AC109 CD54/74ACT109 PDF

    sop65p640

    Abstract: SOP65
    Text: 74AC10, 74ACT10 Triple 3-Input NAND Gate Features General Description • ICC reduced by 50% on 74AC only The AC/ACT10 contains three, 3-input NAND gates. ■ Outputs source/sink 24mA Ordering Information Order Number Package Number 74AC10SC 74AC10SJ 74AC10MTC


    Original     		74AC10, 74ACT10 AC/ACT10 74AC10SC 74AC10SJ 74AC10MTC MTC14 14-Lead MS-012, sop65p640 SOP65 PDF

    ZD302

    Abstract: No abstract text available
    Text: 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to C q Clear sets Q to LOW level T h e AC /AC T109 consists of two_ high-speed com pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall tim es of th e clock


    OCR Scan     		74AC109 74ACT109 ZD302 PDF

    Untitled

    Abstract: No abstract text available
    Text: M O TO R O LA MC74A C 109 74ACT109 D ual J K P o sitiv e Ed ge-Trig gered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of tw o high-speed completely Independent transition clocked JK flip-flops. The clocking operation is independent o f rise and


    OCR Scan     		MC74A MC74ACT109 MC74AC109/74ACT109 MC74AC74/74ACT74 ACT109 74ACT PDF

    Untitled

    Abstract: No abstract text available
    Text: March 1993 Semiconductor 54AC/74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The ’AC /’ACT10 contains three, 3-input NAND gates. • Ice reduced by 50% on 54AC/74AC only ■ Outputs source/sink 24 mA ■ Standard Military Drawing SMD


    OCR Scan     		54AC/74AC10 74ACT10 ACT10 54AC/74AC 54ACT10 54ACTQ10 75/Printed 20-3A PDF

    Untitled

    Abstract: No abstract text available
    Text: Revised October 1998 j,f > i '' ^ : 3? •? » 74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The AC/ACT10 contains three, 3-input NAND gates. ■ lc c reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Order Number


    OCR Scan     		74AC10 74ACT10 AC/ACT10 14-Lead MS-120, 74AC1OSC 74AC1OSJ 74AC1OMTC MTC14 PDF

    Untitled

    Abstract: No abstract text available
    Text: AC1010 • ACT1010 54AC/74 AC 1010 • 54ACT/74ACT1010 16 x 16 Parallel Multiplier/Accumulator Description Connection Diagrams The ’AC/’ACT1010 is a high-speed, low-power 16 x 16 bit parallel m ultiplier with a 35-bit accumulator that is ideally suited for real-time


    OCR Scan     		AC1010 ACT1010 54AC/74 54ACT/74ACT1010 35-bit TDC1010; PDF