74 LS 14 LOGIC DIAGRAM Search Results

MC74F195

Contextual Info: MC74F195 4-BIT PARALLEL ACCESS SHIFT REGISTER The functional characteristics of the MC74F195 4-Bit Parallel Access Shift Register are indicated in the Logic Diagram and Function Table. The device is useful in a wide variety of shifting, counting, and storage applications. It performs serial, parallel, serial-to-parallel, or parallel-to-serial data transfers at

Contextual Info: M MOTOROLA MC74F195 4-BIT PARALLEL A C C E S S SHIFT R EG IST ER The functional characteristics of the MC74F195 4-Bit Parallel Access Shift Register are indicated in the Logic Diagram and Function Table. The device is useful in a wide variety of shifting, counting, and storage applications. It per­

751A-02

Abstract: H12Y 74f51
Contextual Info: MC54/74F51 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE CONNECTION DIAGRAM VCC 1C 1B 1F 1E 1D 1Y 14 13 12 11 10 9 8 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE FAST SCHOTTKY TTL 1 2 3 4 5 6 7 1A 2A 2B 2C 2D 2Y GND J SUFFIX CERAMIC CASE 632-08

Contextual Info: M M O T O R O L A MC74F195 4-BIT PARALLEL ACCESS SHIFT REGISTER The functional characteristics of the MC74F195 4-Bit Parallel Access Shift Register are indicated in the Logic Diagram and Function Table. The device is useful in a wide variety of shifting, counting, and storage applications. It per­

Flip-Flop 7470

Contextual Info: NATIONAL SEtlICOND {LOGIC ? 02E D | bSüllEÉ □ □t.370b 1 I > T -y & 'û 7'ô 7 70 CONNECTION DIAGRAMS PINOUT A 54/7470 JK EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The'70 is a gated input edge-triggeredjJK flip-flop offering Direct Clear and Set inputs, and complementary Q and Q outputs. Informa­

1032E

Contextual Info: LeadFree Package Options Available! ispLSI 1032E In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates Output Routing Pool — 64 I/O Pins, Eight Dedicated Inputs D7 D6 D5 D4 D3 D2 D1 D0

1032E

Abstract: IN5384 EWD18
Contextual Info: ispLSI 1032E In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

74AS871

Contextual Info: TEXAS INSTR LOGIC NOTICE SEE ORDER OF DATA FOR ERRATA ESE D • fiU17S3 QOflBTEE 1 ■ T-Vg-0?-0? S N 5 4 A LS 8 70 , SN 5 4AS 8 70 , S N 5 4 A LS 8 71, SN 5 4 A S 8 71 S N 74 A LS 8 70 , S N 74 A S 8 70 , S N 7 4 A L S 8 7 1 , S N 74 A S 8 71 INFORMATION

74ls157

Abstract: 1251U
Contextual Info: <8> MOTOROLA SN54/74LS157 D E S C R IP T IO N — The LS T T L /M S IS N 5 4 LS /7 4 LS 1 57 is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected data in the true non-inverted form. The

74LS75

Contextual Info: M M O T O R O LA SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTUMSI SN54/74LS75 and SN54/74LS77 are latches used as tem­ porary storage for binary information between processing units and input/out­ put or indicator units. Information present at a data (D) input is transferred to

74LS75

Abstract: 74LS77 751A-02 74ls771 74LS75D
Contextual Info: SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data D input is transferred to

74LS75

Abstract: 74LS77 Equivalent 74LS75 74LS75D notes on 74LS75 751A-02 truth table NOT gate 74 TW 20-UL q1134
Contextual Info: SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI SN54/ 74LS75 and SN54/ 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data D input is transferred to

74LS192

Abstract: 74LS192 PIN diagram 74LS192 truth table 74LS193 pin data 74ls193 pin diagram TTL 74ls193 74LS193 truth table 74LS192 INTERNAL DIAGRAM 74LS192 table 74LS193
Contextual Info: SN54/74LS192 SN54/74LS193 PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER PRESETTABLE BCD / DECADE UP/ DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade 8421 Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate

258B DIODE

Abstract: LS257B Motorola Zc 34
Contextual Info: M MOTOROLA QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The LS TTL/M SI SM 54/74LS257B and the SN 54/74LS 258B are Quad 2-Input Multiplexers with 3-state outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present

LS575

Abstract: SN74ALS574 74AS574
Contextual Info: T YP E S S N 54ALS5 74, SN 54ALS5 75 . S N 5 4AS 5 74 , SN54AS575 S N 7 4 A L S 5 7 4 , S N 74 A L S 5 7 5 , S N 7 4 A S 5 7 4 , SN 74A S 5 75 O CTAL D T Y P E EDGE TRIGGERED FLIP FLOP S WITH 3-STATE OUTPUTS D 2661, JUNE 1982 —REVISED DECEMBER 1983 3-S tate Buffer-Type Noninverting Outputs Drive

Contextual Info: M M O T O R O L A Military 54LS133 13-lnput NAND Gate ELECTRICALLY TESTED PER: MPG54LS133 MPO mini LOGIC DIAGRAM V cc N M L K J H AVAILABLE AS: Y 1) JAN: N/A 2) SMD: N/A 3)883: 54LS133/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: E CERFLAT: F LCC: 2

LS157

Contextual Info: M M O T O R O L A . SN54/74LS157 QUAD 2-INPUT MULTIPLEXER The LS TTL/M SI S N 54/74LS 157 is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected data in the

ls378

Abstract: 74LS377 74LS174 74LS175 74LS378 74LS379
Contextual Info: SN54/74LS377 SN54/74LS378 SN54/74LS379 OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a

74LS181

Abstract: alu 74ls181 SN54LSXXXJ SN74LSXXXN sn5474ls181
Contextual Info: SN54/74LS181 4-BIT ARITHMETIC LOGIC UNIT The SN54 / 74LS181 is a 4-bit Arithmetic Logic Unit ALU which can perform all the possible 16 logic, operations on two variables and a variety of arithmetic operations. 4-BIT ARITHMETIC LOGIC UNIT • Provides 16 Arithmetic Operations Add, Subtract, Compare, Double,

alu 74ls181

Abstract: 74LS181 74LS181 alu 5Bp power control datasheet 74LS181 arithmetic logic unit datasheet SN54LSXXXJ SN74LSXXXN ls181
Contextual Info: SN54/74LS181 4-BIT ARITHMETIC LOGIC UNIT The SN54 / 74LS181 is a 4-bit Arithmetic Logic Unit ALU which can perform all the possible 16 logic, operations on two variables and a variety of arithmetic operations. 4-BIT ARITHMETIC LOGIC UNIT • Provides 16 Arithmetic Operations Add, Subtract, Compare, Double,

Contextual Info: SN54ALS168B, SN54ALS169B, SN54AS168, SN54AS169 S N 74 A LS 16 8 B , S N 74 A LS 16 9 B , S N 74 A S 16 8 , S N 74AS16 9 SYNCHRONOUS 4-BIT UP/DOWN DECADE A N D BINARY COUNTERS M AR C H 1 9 8 4 - • • I Fully Synchronous Operation for Counting and Programming

74LS190 PIN diagram

Abstract: 74LS190 up down decade counter truth table of 74LS190 74LS191 datasheet 74LS190 pins 74LS190 74LS190 APPLICATIONS 74LS191 LS191 74LS190 application
Contextual Info: SN54/74LS190 SN54/74LS191 PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade 8421 Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16 Binary Counter. State changes of the counters are synchronous with the

74 LS 151 Logic DIAGRAM

Abstract: 74LS151 multiplexer truth table 74LS151 truth table
Contextual Info: M M O T O R O L A SN54/74LS151 8-INPUT MULTIPLEXER The TTL/MSI SN5 4 / 74 LS 151 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS 151 can be used as a universal function generator to

74LS283 truth table

Abstract: 74ls283 datasheet LS 74LS283 74LS283 74LS283 dip Ls283 74LS283 pin diagram truth table NOT gate 74 16C4 SN54LSXXXJ
Contextual Info: SN54/74LS283 4-BIT BINARY FULL ADDER WITH FAST CARRY The SN54 / 74LS283 is a high-speed 4-Bit Binary Full Adder with internal carry lookahead. It accepts two 4-bit binary words A1 – A4, B 1 – B4 and a Carry Input (C0). It generates the binary Sum outputs (∑1 – ∑4) and the Carry