74LS77 Search Results

74LS75

Abstract: 74LS77 Equivalent 74LS75 74LS75D notes on 74LS75 751A-02 truth table NOT gate 74 TW 20-UL q1134
Contextual Info: SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI SN54/ 74LS75 and SN54/ 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data D input is transferred to

74LS75

Contextual Info: M M O T O R O L A SN54/74LS75 SN54/74LS77 D E S C R IP T IO N — T h e T T L /M S I S N 5 4 L S / 7 4 L S 7 5 an c*S N 5 4 LS /7 4 LS 7 7 are latch es used as tem porary storage for binary information between processing u n itsa n d input/output or indicator units. Inform ation present

74LS75

Contextual Info: M M O T O R O L A SN54LS/74LS75 SN54LS/74LS77 D E S C R IP T IO N — The TT L/M S IS N 54LS /74LS 75 and SN 54LS /74LS77 are latches used as tem porary storage for binary inform ation between processing units and in p u t/o u tp u t or indicator units, inform ation present

74LS75

Abstract: 74LS77 751A-02 74ls771 74LS75D
Contextual Info: SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data D input is transferred to

1S2074

Abstract: 74LSOO HD74LS77 Hitachi Scans-001
Contextual Info: • 4 - b i t Bistable Latches IP IN ARRANGEMENT The H D 74LS77 is ideally suited for use as temporary storage for binary information between processing units and input/ output or indicator units. Information present at a data D input is transferred to the Q output when the enable (G) is

74LS75

Contextual Info: M M O T O R O LA SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTUMSI SN54/74LS75 and SN54/74LS77 are latches used as tem­ porary storage for binary information between processing units and input/out­ put or indicator units. Information present at a data (D) input is transferred to

74LS75

Contextual Info: M M O T O R O L A SN54LS/74LS75 SN54LS/74LS77 D ESC R IPTIO N — TheTTL/M S I S N 54LS/74LS75 and SN 54LS/74LS 77 are latches used as tem porary storage for binary inform ation between processing u nits and in p u t/o u tp u t or indicator units. Inform ation present

pin DIAGRAM OF IC 74ls75

Abstract: 74LS75 logic Ic 74
Contextual Info: M M O T O R O L A SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI S N 54/74LS 75 and S N 54/74LS 77 are latches used as tem ­ porary storage for binary information between processing units and input/out­ put or indicator units. Information present at a data (D) input is transferred to

Contextual Info: TC74HC77AP/AF 4 -B IT D TYPE LATCH The TC74HC77A is a high speed CMOS 4-B IT D -T Y P E LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation sim ilar to equivalent LSTTL while m aintaining the CMOS low power dissiparion.

Contextual Info: TOSHIBA TC74HC77AP/AF 4-Bit D Type Latch TheTC74HC77A is a high speed CMOS 4-BIT D-TYPE LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

CI 7474

Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °

C350AVB

Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
Contextual Info: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices

CI 7446

Abstract: CI 74141 cI 74ls47 CI 7447 CI 7448 ci 7445 7-seg ANODE COMMON CI 74LS48 TTL 7446 BCD D147
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 i Ao A RBO a A 2 b A3 e d 1 El e 13 12 11 10 RBI f 9 E 9 15 3 2 4 m l 14 6 m Do MR TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

Contextual Info: M54HC77 M74HC77 / = 7 SGS-THOMSON 4-BIT D-TYPE LATCH • HIGH SPEED tpD = 15 ns TYP. at VCc = 5V ■ LOW POWER DISSIPATION lCc = 2 ¡¡A (MAX.) at TA = 25°C Î ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 »/o VCC (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram ic 74109 74LS107 74109 dual JK IC 74196 7476 Connection diagram 74LS109 ic 7474 pin diagram 7474 D latch
Contextual Info: IO PO 10 ro o CO 00 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch - o to Item 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit RS Latch 4-Bit RS Latch 4-Bit RS Latch 4-Bit RS Latch 5477 54/7475 93L14 9314

74HC77

Abstract: 54HC SGS 54HC 10168 74HC series 74HC M54HC77 M74HC77 74LS77
Contextual Info: SGS-THOMSON M54HC77 M74HC77 H i iM K l© S 4-BIT D-TYPE LATCH • HIGH SPEED tpo = 15 ns (TYP. at V c c = 5V ■ LOW POWER DISSIPATION Ice = 2 /iA (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY VNIH = VNil = 28% VCC (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

7054F

Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Contextual Info: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver

Contextual Info: rz 7 scs-ntoMsoN GMra H[Li *S ¡¡5ÎÎÎSÏÏ “ 7# M74HC77 4-BIT D-TYPE LATCH • HIGH SPEED t p D = 10 ns TYP. AT VCc = 5 V ■ LOW POWER DISSIPATION Ice = 2 nA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY Vnih = V nil = 28 % Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher