AZ 280 chip
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. 32K x 32, 3.3V SYNCHRONOUS SRAM WITH 3.3V/2.5V PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER FEATURES: • 32K x 32 memory configuration • Supports high performance system speed - up to 133 MHz 4.5ns Clock-to-Data Access in Pipelined Mode
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PDF
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100-pin
IDT71V532
71V532
PK100-1)
AZ 280 chip
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AZ 280 chip
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. 32K x 32, 3.3V SYNCHRONOUS SRAM WITH 3.3V/2.5V PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER FEATURES: PRELIMINARY 71V532 The 71V532 SRAM contains write, data, address, and control registers. Internal logic allows the SRAM to generate
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Original
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PDF
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IDT71V532
IDT71V532
71V532
PK100-1)
AZ 280 chip
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Untitled
Abstract: No abstract text available
Text: 32K x 32, 3.3V SYNCHRONOUS SRAM WITH 3.3V/2.5V PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER Integrated D evice Technology, Inc. FEATURES: PRELIMINARY 71V532 The 71V532 SRAM contains write, data, address, and control registers. Internal logic allows the SRAM to generate
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OCR Scan
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PDF
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IDT71V532
100-pin
IDT71BP,
492-M
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71V532
Abstract: IN3616
Text: 32K x 32, 3.3V SYNCHRONOUS SRAM WITH 3.3V/2.5V PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER FEATURES: PRELIMINARY 71V532 The 71V532 SRAM contains write, data, address, and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until
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OCR Scan
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PDF
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100-pin
IDT71V532
IDT71V532
576-bit
71V532
PK100-1)
IN3616
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