62A2016 Search Results

Contextual Info: 62A2016 Series Preliminary Dual 8,192-Word x 20-Bit Static Cache Memory • DESCRIPTION The 62A2016 is a high speed 327,680-bit cache memory organized as two banks of 8,192 words by 20-bits. The device includes dual address latches, dual chip select latches, data multiplexer

Contextual Info: 62A2016 Series- P relim inary Dual 8,192-Word x 20-Bit Static Cache Memory • DESCRIPTION The 62A2016 is a high speed 327,680-bit cache memory organized as tw o banks of 8,192 words by 20-bits. The device includes dual address latches, dual chip select latches, data multiplexer

MIPS R3000

Abstract: MIPS R3000A
Contextual Info: 62A2016 Series -P relim inary Dual 8,192-Word x 20-Bit Static Cache Memory • DESCRIPTIO N The H M 62A 2016 is a high speed 3 2 7 ,6 8 0 -b it cache m em ory organized as tw o banks o f 8,192 w ords by 20-bits. The device includes dual address latches, duai ch ip select latches, data m ultiplexer

Contextual Info: b lE ]> • 44clbECI3 OOPlbSO SbT ■ H I T S 62A2016/2017 Series T - ^ 6 - 2 .3 - 1 2 - Dual 8192-word x 20-bit Static Cache Memory H IT A C H I/ LOGIC/ARRAYS/MEM The 62A2016/2017 is a high speed 327680-bit cache memory organized as two banks of 8192