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    Texas Instruments 54ACT11030J

    NAND GATE; Temperature Grade: MILITARY; Terminal Form: THROUGH-HOLE; No. of Terminals: 14; Package Code: DIP; Package Shape: RECTANGULAR;
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    Vyrian 54ACT11030J 201
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    Texas Instruments 54ACT11030FK

    NAND GATE; Temperature Grade: MILITARY; Terminal Form: NO LEAD; No. of Terminals: 20; Package Code: QCCN; Package Shape: SQUARE;
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    Vyrian 54ACT11030FK 89
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    54ACT11030 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54ACT11030 Texas Instruments 8-INPUT POSITIVE-NAND GATES Original PDF
    54ACT11030 Texas Instruments 8-INPUT POSITIVE-NAND GATES Original PDF
    54ACT11030FK Texas Instruments 8-Input Positive-NAND Gate Original PDF
    54ACT11030J Texas Instruments 8-INPUT POSITIVE-NAND GATES Original PDF

    54ACT11030 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout


    Original     		54ACT11030, 74ACT11030 SCLS050 500-mA 300-mil 54ACT11030 74ACT11030 PDF

    54ACT11030

    Abstract: 74ACT11030 74ACT11030DR
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout


    Original     		54ACT11030, 74ACT11030 SCLS050 54ACT11030 500-mA 300-mil 54ACT11030 74ACT11030 74ACT11030DR PDF

    54ACT11030

    Abstract: 74ACT11030
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout


    Original     		54ACT11030, 74ACT11030 SCLS050 54ACT11030 500-mA 300-mil 54ACT11030 74ACT11030 PDF

    74ACT11030D

    Abstract: No abstract text available
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout


    Original     		54ACT11030, 74ACT11030 SCLS050 500-mA 300-mil 54ACT11030 74ACT11030 74ACT11030D PDF

    54ACT11030

    Abstract: 74ACT11030 74ACT11030DR
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout


    Original     		54ACT11030, 74ACT11030 SCLS050 54ACT11030 500-mA 300-mil 54ACT11030 74ACT11030 74ACT11030DR PDF

    54ACT11030

    Abstract: 74ACT11030 y12e
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout


    Original     		54ACT11030, 74ACT11030 SCLS050 54ACT11030 500-mA 300-mil 54ACT11030 74ACT11030 y12e PDF

    D2957

    Abstract: 1987-REVISEDAPRIL
    Text: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted


    OCR Scan     		54ACT11030 74ACT11030 D2957. 1987-REVISEDAPRIL 500-mA 300-mll D2957, D2957 PDF

    54AC11030

    Abstract: 54ACT11030 74AC11030 74ACT11030 D2957
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES TI0059— D2957, MARCH 1987— REVISED M ARCH 1990 54A C T11030 I PACKAGE 74ACT11030 . . . D OR N PACKAGE Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout TOP VIEW Center-Pin V q c and GND Configurations to


    OCR Scan     		54ACT11030, 74ACT11030 TI0059â D2957, 500-mA 300-mil 54ACT11030 54AC11030 74AC11030 74ACT11030 D2957 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES TI0059— D2957, MARCH 1987— REVISED MARCH 1990 54ACT11030 . . . J PACKAGE 74ACT11030 . . D OR N PACKAGE • Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout TOP VIEW


    OCR Scan     		54ACT11030, 74ACT11030 TI0059-- D2957, 500-mA 300-mil 54ACT11030 74ACT11030 JL15V PDF