48CSP Search Results

Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 Add 48CSP-6x8mm package outline Mar. 08, 2005 2.2 Revise 48CSP-8x10mm pkg code from W to K

Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. 2.0 2.1 History Issue Date Initial issue with new naming rule Feb.15, 2005 Add 48CSP-6x8mm package outline Mar. 08.2005 Remark 1 Rev. 2.1 Chiplus reserves the right to change product or specification without notice.

CS16LV81923

Abstract: 850C SRAM 512K
Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 Add 48CSP-6x8mm package outline Mar. 08, 2005 2.2 Revise 48CSP-8x10mm pkg code from W to K

Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. 2.0 2.1 History Issue Date Initial issue with new naming rule Feb.15, 2005 Add 48CSP-6x8mm package outline Mar. 08.2005 Remark 1 Rev. 2.1 Chiplus reserves the right to change product or specification without notice.

Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 Add 48CSP-6x8mm package outline Mar. 08, 2005 2.2 Revise 48CSP-8x10mm pkg code from W to K

Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 Add 48CSP-6x8mm package outline Mar. 08, 2005 2.2 Revise 48CSP-8x10mm pkg code from W to K

Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 Add 48CSP-6x8mm package outline Mar. 08, 2005 2.2 Revise 48CSP-8x10mm pkg code from W to K

Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 Add 48CSP-6x8mm package outline Mar. 08, 2005 2.2 Revise 48CSP-8x10mm pkg code from W to K

Contextual Info: High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. 2.0 2.1 2.2 History Initial issue with new naming rule Add 48CSP-6x8mm package outline Revise 48CSP-8x10mm pkg code from W to K Issue Date Feb.15, 2005 Mar. 08, 2005

Contextual Info: Advance information Features • Intelliw att active p o w e r red u ction circuitry • Easy m em o r y exp an sion w ith CEI, CE2, OË in p uts • 1.6 5 V to 1.9 5 V op eratin g range 0ESD 8 -7 • TTL/LVTTL-com patible, three-state I /O • JEDEC registered packaging

Contextual Info: A Advance information •■ 7C254096LL 2.5V 512K x8 IntelliwatT low power CMOS SRAM Features • • • • • Organization: 524,288 w ords x 8 bits Intelliwatt active pow er circuitry 2.3V to 3.0V operating range 2 5 /3 5 /5 5 /7 0 /1 0 0 ns address access tim e

AS6UA25616

Abstract: AS6UA25616-BC
Contextual Info: October 2000 AS6UA25616 2.3V to 3.6V 256Kx16 Intelliwatt low-power CMOS SRAM with one chip enable • Low power consumption: STANDBY - 72 µW max at 3.6V - 41 µW max at 2.7V • 1.2V data retention • Equal access and cycle times • Easy memory expansion with CS, OE inputs

Contextual Info: Preliminary information •■ AS7C251024LL A 2.5V 128K X 8 lntelliwatt,v low power CM O S SRAM Features • • • • Intelliwatt active power reduction circuitry 2.3V to 3.0V operating range Organization: 131,072 words x 8 bits High speed - 5 5 * /7 0 /1 0 0 ns address access time

Contextual Info: H ig h p e r f o r m a n c e 6 4 K X 16 C M O S SR AM A S7C 31026L L 6 4 K X 16 In telliw att low power CMOS SRAM Advance information • • • • • Optimized design for battery operated portable systems Intelliwatt™ active pow er reduction circuitry

100-PIN TQFP XILINX DIMENSION

Abstract: xilinx xc9536 digital clock xc9536-pc44 XC95216XL xc95144 pin diagram XC95108XL XC9536 XC95144 XC9500 pinout XC9536XL Series
Contextual Info: Ann Duft Xilinx, Inc. 408 879-4726 publicrelations@xilinx.com Kathy Keller Oak Ridge Public Relations (408) 253-5042 kathy.keller@oakridge.com FOR IMMEDIATE RELEASE XILINX ANNOUNCES NEWEST MEMBER OF INDUSTRY’S FASTEST GROWING CPLD FAMILY New XC95144 device targets sweet spot of ISP CPLD market with lowest price per macrocell

K6R1016C10

Abstract: k6r1016c1c
Contextual Info: K6R1016C1C-C/C-L, K6R1016C1C-I/C-P CMOS SRAM Document Title 64Kx16 Bit High-Speed CMOS Static RAM 5.0V Operating . Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release with preliminary.

Contextual Info: KM616FS4010 Family CMOS SRAM Document Title 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft April 2, 1998 Advance 1.0 Finalize - DC characteristics change ICC1 : 3mA → 4mA

Contextual Info: $GYDQFHLQIRUPDWLRQ $6&// 9.ð,QWHOOLZDWWŒORZSRZHU&02665$0 HDWXUHV • Smallest footprint packages - 48 ball FBGA - 400 mil 44-pin TSOP II • Center power and ground pins for low noise • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA

KM68FR1000AFI-10

Abstract: KM68FR1000AFI-7 KM68FR1000ATGI-10 KM68FR1000ATGI-7
Contextual Info: Advance KM68FR1000A Family CMOS SRAM Document Title 128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM Revision History Revision No. 0.0 History Draft Data Remark Design target November 3, 1998 Advance The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

Contextual Info: K6R1016V1C-C/C-L, K6R1016V1C-I/C-P for AT&T CMOS SRAM Document Title 64Kx16 Bit High-Speed CMOS Static RAM 3.3V Operating Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release with Preliminary.

Contextual Info: $GYDQFHLQIRUPDWLRQ $6&// 9.ð,QWHOOLZDWWŒORZSRZHU&02665$0 HDWXUHV • Smallest footprint packages - 48 ball FBGA - 400 mil TSOP II • Center power and ground pins for low noise • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA

Contextual Info: KM616FS2010A Family CMOS SRAM Document Title 128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark Advance 0.0 Initial Draft June 25, 1998 1.0 Finalize - IDR test condition change: Vcc=1.5V to Vcc=1.2V

Contextual Info: KM616FR4010 Family Advance CMOS SRAM Document Title 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft April 2, 1998 Advance 0.1 Revise Speed bin change : 70/100ns —> 85/100ns

Contextual Info: Advance CMOS SRAM KM68FU2000A Family Document Title 256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial Draft Draft Date Remark July 9, 1998 Advance The attached datasheets are provided by SAM SU NG Electronics. S AM SU NG Electronics C O., LTD. reserve the right to change the specifications and