400MBS Search Results

Contextual Info: FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Receiver Features Description ̇ ̇ ̇ ̇ ̇ ̇ ̇ Greater than 400Mbs Data Rate This dual receiver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS

SOIC127P600X175-8M

Abstract: M08AREV13 FIN1027 FIN1028 FIN1028M FIN1028MX JESD22-A114 JESD22-A115 SOIC127P600X175 Fairchild DUAL receiver
Contextual Info: FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Receiver Features Description ƒ ƒ ƒ ƒ ƒ ƒ ƒ Greater than 400Mbs Data Rate This dual receiver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS

Contextual Info: Preliminary Revised February 2002 FIN1002 LVDS 1-Bit High Speed Differential Receiver Preliminary General Description Features This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal

Contextual Info: Revised June 2001 FIN1047 3.3V LVDS 4-Bit Flow-Through High Speed Differential Driver General Description Features This quad driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350mV which

Contextual Info: W3H32M72E-XSB2X W3H32M72E-XSB2XF 256MB – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES BENEFITS  Data rate = 667, 533, 400  69% space savings vs. FPBGA  Package:  Reduced part count • 208 Plastic Ball Grid Array PBGA , 16 x 20mm

Contextual Info: W3H264M16E-XBX ADVANCED* 256MB – 2 x 64M x 16 DDR2 SDRAM 79 PBGA FEATURES BENEFITS  Data rate = 400 Mb/s, 533 Mb/s, 667 Mb/s*  Larger ball pitch for higher reliability  Package:  Footprint compatible with W3H64M16E • 79 Plastic Ball Grid Array PBGA , 11 x 14mm

DNU-A13

Contextual Info: W3H64M16E-XBX 128MB – 64M x 16 DDR2 SDRAM 79 PBGA FEATURES BENEFITS  Data rate = 400 Mb/s, 533 Mb/s  Larger ball pitch for higher reliability  Package:  Pinout compatible with 2-Rank Version • 79 Plastic Ball Grid Array PBGA , 11 x 14mm

W3H32M72E-XSBX

Abstract: calibration definition
Contextual Info: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Programmable CAS latency: 3, 4, 5, or 6 Package: Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

us8 Package FAIRCHILD

Abstract: FI1018K8X FI1018M FI1018MX M08A
Contextual Info: Preliminary Revised December 2000 FI1018 3.3V LVDS Single High Speed Differential Receiver Preliminary General Description Features This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal

FI1531M

Abstract: FI1531MTC M16A MTC16
Contextual Info: Preliminary Revised December 2000 FI1531 5V LVDS Quad High Speed Differential Driver Preliminary General Description Features This quad driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350 mV which

Contextual Info: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

Contextual Info: White Electronic Designs W3H32M64E-XSBX ADVANCED* 32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Programmable CAS latency: 3, 4 or 5 Package: Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 20mm

Contextual Info: White Electronic Designs W3H32M64E-XSBX 32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Write latency = Read latency - 1* tCK „ Package: „ Commercial, Industrial and Military Temperature Ranges „ Organized as 32M x 64, user configurable as 2 x

W3H32M72E

Abstract: BA0BA12
Contextual Info: White Electronic Designs W3H32M72E-XSBX 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Programmable CAS latency: 3, 4, 5, or 6  Package:  Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

W3H128M72

Abstract: W3H128M72E-XSBX W3H128M72E
Contextual Info: White Electronic Designs W3H128M72E-XSBX Advanced* 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Package: „ CK/CK# Termination options available • 0 ohm, 20 ohm • 208 Plastic Ball Grid Array PBGA , 16 x 22mm

W3H32M72E

Contextual Info: White Electronic Designs W3H32M72E-XSB2X Preliminary 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Programmable CAS latency: 3, 4, 5, or 6  Package:  Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 20mm

Contextual Info: White Electronic Designs W3H32M72E-XSBX * 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

W3H64M64E

Contextual Info: White Electronic Designs W3H64M64E-XSBX 64M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Write latency = Read latency - 1* tCK „ Package: „ Commercial, Industrial and Military Temperature Ranges • 1.0mm pitch „

AS4DDR264M72PBG

Abstract: H11M1
Contextual Info: iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • Proprietary Enchanced Die Stacked iPEM

FIN1531

Abstract: FIN1532 FIN1531M FIN1531MTC M16A MTC16
Contextual Info: Preliminary Revised February 2001 FIN1531 5V LVDS 4-Bit High Speed Differential Driver Preliminary General Description Features This quad driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350 mV which

FIN1532

Abstract: FIN1532MTC M16A MTC16 FIN1531 FIN1532M
Contextual Info: Preliminary Revised February 2001 FIN1532 5V LVDS 4-Bit High Speed Differential Receiver Preliminary General Description Features This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal

FIN1031

Abstract: FIN1031M FIN1031MTC FIN1032 M16A MTC16
Contextual Info: Preliminary Revised February 2001 FIN1031 3.3V LVDS 4-Bit High Speed Differential Driver Preliminary General Description Features This quad driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350mV which

MTC16

Abstract: FIN1031 FIN1032 FIN1032M FIN1032MTC M16A
Contextual Info: Preliminary Revised February 2001 FIN1032 3.3V LVDS 4-Bit High Speed Differential Receiver Preliminary General Description Features This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels.

FIN1019

Abstract: FIN1019M FIN1019MTC M14A MTC14
Contextual Info: Revised April 2001 FIN1019 3.3V LVDS High Speed Differential Driver/Receiver General Description Features This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The driver translates LVTTL signals to