TXC10 M 60
Abstract: 10BASE2 10BASE5 93LC46B FPT-144P-M08 MB86961A MB86974 NM93C46
Text: PAUSE FLOW CONTROL 10Mb/s-/100Mb/s Ethernet Controller MB86974 Package • 144-pin, plastic QFP • FPT-144P-M08 Description The Fujitsu MB86974 is a high-quality Ethernet controller that offers many benefits and advantages to its users. The controller operates at either 100-Mbit/s or 10-Mbit/s, and
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10Mb/s-/100Mb/s
MB86974
144-pin,
FPT-144P-M08
MB86974
100-Mbit/s
10-Mbit/s,
LAN-DS-20654-8/98
TXC10 M 60
10BASE2
10BASE5
93LC46B
FPT-144P-M08
MB86961A
NM93C46
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rx2 99
Abstract: 93c46l 93c46li 16C550 AD29 AD30 XR17V258 bu 515 144LQFP 16550
Text: XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT AUGUST 2010 REV. 1.0.2 GENERAL DESCRIPTION The XR17V2581 V258 is a single chip 8-channel 66MHz PCI (Peripheral Component Interconnect) UART (Universal Asynchronous Receiver and Transmitter)
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XR17V258
66MHZ
XR17V2581
32-bit
33MHz
rx2 99
93c46l
93c46li
16C550
AD29
AD30
XR17V258
bu 515
144LQFP
16550
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Untitled
Abstract: No abstract text available
Text: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Introduction • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI
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V320USC
32-Bit
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54SX32
Abstract: A54SX32 A54SX32A A54SX72A PAR64 REQ64 54SX32A il 074
Text: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
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TCI D2S
Abstract: TCI D2S f BRA16 128-Byte CSR19 M1FD STMicroelectronics BET
Text: STE10/100 PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY PRODUCT PREVIEW 1.0 DESCRIPTION The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to
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STE10/100
STE10/100
10BASE-T
100BASE-TX
32-bit
IEEE802
TCI D2S
TCI D2S f
BRA16
128-Byte
CSR19
M1FD
STMicroelectronics BET
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intel 82596
Abstract: 82559 Reference Manual 82559 LF8200A Three-Five 1229H 82557 user manual 82557 TCP 8118
Text: 82559 Fast Ethernet* Multifunction PCI/ CardBus Controller Networking Silicon Datasheet Product Features • ■ Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — Glueless 32-bit PCI master interface
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10BASE-T
100BASE-TX
32-bit
15mm2
FLA15/
FLA12
FLA11
FLA14/
FLA10
FLA16
intel 82596
82559 Reference Manual
82559
LF8200A
Three-Five
1229H
82557 user manual
82557
TCP 8118
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PDF
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PQFP128
Abstract: 93C46 PC99 ci 9410 HB626-1 IBM REV 2.8 TCI D2S
Text: STE10/100A PCI 10/100 Ethernet controller with integrated PHY 3.3V Features • IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant ■ Support for IEEE802.3x flow control ■ IEEE802.3u auto-negotiation support for 10BASE-T and 100BASE-TX ■ PCI bus interface rev. 2.2 compliant
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STE10/100A
IEEE802
100BASE-TX
10BASE-T
100BASE-TX
32-bit
PQFP128
93C46
PC99
ci 9410
HB626-1
IBM REV 2.8
TCI D2S
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AD27
Abstract: AD29 V320USC V320USC-75 AD1485
Text: DS-UC01-0102.fm Page 1 Wednesday, June 30, 1999 7:30 PM Datasheet V320USC Universal System Controller PCI System Controller for 32-Bit MIPS and SuperH™ System Interface • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus
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DS-UC01-0102
V320USC
32-Bit
DS-UC01-0102
AD27
AD29
V320USC-75
AD1485
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TDA 7378
Abstract: TDA 7822 block diagram baugh-wooley multiplier tda 12062 equivalent for tda 4858 ic free transistor equivalent book STD-80 4856 a 14 PIN DIP W908 LSI CMOS Technology
Text: D • A • T • A • B • O • O • K STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library April 1997 V SAMSUNG SAMSUNG ASIC STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library Data Book 1997 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior
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STD80/STDM80
notice10.
TDA 7378
TDA 7822
block diagram baugh-wooley multiplier
tda 12062
equivalent for tda 4858 ic
free transistor equivalent book
STD-80
4856 a
14 PIN DIP W908
LSI CMOS Technology
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Untitled
Abstract: No abstract text available
Text: 82551IT Fast Ethernet PCI Controller Networking Silicon - 82551IT Datasheet Product Features • ■ ■ ■ ■ ■ ■ Enhanced IP Protocol Support — TCP, UDP, IPv4 checksum offload — Received checksum verification Quality of Service QoS — Multiple priority transmit queues
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82551IT
82551IT
10BASE-T
100BASE-TX
32-bit
15mm2
FLA16
FLA15/
FLA14/
FLA13/
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Untitled
Abstract: No abstract text available
Text: 82551IT Fast Ethernet PCI Controller Networking Silicon - 82551IT Datasheet Product Features • ■ ■ ■ ■ ■ ■ Enhanced IP Protocol Support — TCP, UDP, IPv4 checksum offload — Received checksum verification Quality of Service QoS — Multiple priority transmit queues
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82551IT
82551IT
10BASE-T
100BASE-TX
32-bit
15mm2
FLA16
FLA15/
FLA14/
FLA13/
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82551it
Abstract: No abstract text available
Text: 82551QM Fast Ethernet Multifunction PCI/CardBus Controller Networking Silicon - 82551QM Datasheet Product Features • ■ ■ ■ ■ ■ ■ Enhanced IP Protocol Support — TCP, UDP, IPv4 Checksum Offload — Received Checksum Verification Quality of Service QoS
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82551QM
82551QM
10BASE-T
100BASE-TX
32-bit
15mm2
82551it
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application notes of TF 513
Abstract: PHSOSCK17 PHSOSCK27 STD130
Text: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)
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STD130
application notes of TF 513
PHSOSCK17
PHSOSCK27
STD130
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CL 2181
Abstract: SL 1088 PHSOSCK17 PHSOSCK27
Text: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)
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STD131
CL 2181
SL 1088
PHSOSCK17
PHSOSCK27
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
RT54SX-S
TM1019
HiRel a54sx72a unused
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rt54sx32su
Abstract: RTSX72 RTSX32SU RTSX72-S
Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
rt54sx32su
RTSX72
RTSX32SU
RTSX72-S
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OB33LN
Abstract: ProASICPLUS Flash Family FPGAs v3.3
Text: v3.3 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process
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APA075,
APA150,
APA300
OB33LN
ProASICPLUS Flash Family FPGAs v3.3
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Untitled
Abstract: No abstract text available
Text: v5.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os
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schematic diagram online UPS for high frequency
Abstract: ag19
Text: v3.3 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process
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APA750
Abstract: GL25 4kx8 sram
Text: v3 .4 PLUS ProASIC TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process
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Untitled
Abstract: No abstract text available
Text: v3.0 SX-A Family FPGAs Leading-Edge P erfo rm an c e • 250 MHz System Performance • 3.8ns Clock-to-Out Pad-to-Pad • 350 MHz Internal Performance S p ec ific atio n s • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins
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22p/0
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rdl 117-a
Abstract: pa-1000b
Text: A d v a n c e d v O .7 ? TM P r o A S IC ^ F la s h F a m ily F P G A s High Performance, Low Skew, Splitable Global Network 100% Routability and Utilization I/O Schmitt-Trigger Option on Every Input Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate
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198kbits
rdl 117-a
pa-1000b
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54sx08
Abstract: THERMAL Fuse m20 tf 115 c
Text: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up
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Untitled
Abstract: No abstract text available
Text: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew
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54SXFamily
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