20G10-25
Abstract: 20G10-30 20G10B-20 20G10B-25 12L10 16L6 18L4 20L10 20L8 20G108
Text: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable — Uses proven EPROM technology • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Fully AC and DC tested
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PLDC20G10B/PLDC20G10
24-Pin
20G10-25
20G10-30
20G10B-20
20G10B-25
12L10
16L6
18L4
20L10
20L8
20G108
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transistor c331
Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
Text: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the
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CY7C331
CY7C331
transistor c331
c331 transistor
C3318
C3317
C331
C3311
C331 datasheet
20HC
c331 equivalent
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12L10
Abstract: 16L6 20L10 20L8 PLDC20G10 PLDC20G10B ULTRA37000
Text: PLDC20G10B PLDC20G10 USE ULTRA37000 FOR ALL NEW DESIGNS CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns
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PLDC20G10B
PLDC20G10
ULTRA37000TM
24-Pin
20L10,
12L10,
PLDC20G10B/PLDC20G10
12L10
16L6
20L10
20L8
PLDC20G10
PLDC20G10B
ULTRA37000
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20G10
Abstract: 20G10B-20 12L10 16L6 18L4 20L10 20L8
Text: fax id: 6014 1P LDC20 G1 0B/P LD C20 G1 0 PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable — Uses proven EPROM technology • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns
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LDC20
PLDC20G10B/PLDC20G10
24-Pin
20G10
20G10B-20
12L10
16L6
18L4
20L10
20L8
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20G10-25
Abstract: 20G10B-15 20G10B-20 Ultra37000TM 12L10 16L6 20L10 20L8 PLDC20G10 PLDC20G10B
Text: PLDC20G10B PLDC20G10 USE ULTRA37000 FOR ALL NEW DESIGNS CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns
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PLDC20G10B
PLDC20G10
ULTRA37000TM
24-Pin
20L10,
12L10,
PLDC20G10B/PLDC20G10
20G10-25
20G10B-15
20G10B-20
12L10
16L6
20L10
20L8
PLDC20G10
PLDC20G10B
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12L10
Abstract: 16L6 18L4 20L10 20L8 20G102 CP 6014 pld20g10
Text: fax id: 6014 1P LDC20 G1 0B/P LD C20 G1 0 PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable — Uses proven EPROM technology • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns
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LDC20
PLDC20G10B/PLDC20G10
24-Pin
12L10
16L6
18L4
20L10
20L8
20G102
CP 6014
pld20g10
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transistor c331
Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
Text: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable
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1CY7C331
CY7C331
transistor c331
c331 transistor
c331
c331 equivalent
C3318
C3319
C3314
c3317
C3311
transistor c331 datasheet
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c331 equivalent
Abstract: C3317 c331-12 c3311 192x pin diagram c331
Text: CY7C331 Asynchronous Registered EPLD • Low power — 90 mA typical ICC quiescent Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the I/O
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CY7C331
28-pin
c331 equivalent
C3317
c331-12
c3311
192x
pin diagram c331
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Untitled
Abstract: No abstract text available
Text: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin
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28-pin
28-pin
termW22
28-Lead
300-Mil)
CY7C331
001305b
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AC-231
Abstract: No abstract text available
Text: CY7B201 PRELIMINARY s CYPRESS . r SEMICONDUCTOR Reprogrammable 128K x 8 Power-Down PROM Features Functional Description • BiFAMOS for optimum speed/ power The CY7B201 is a high-performance 1-megabit BiFAMOS PROM organized in 128 Kbytes. It is available in 32-pin,
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CY7B201
32-pin,
600-mil
32-pin
CY7B201
CY7B201â
AC-231
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Untitled
Abstract: No abstract text available
Text: CY7B210 PRELIMINARY CYPRESS SEMICONDUCTOR Features Product Characteristics • BiFAMOS for optimum speed/ power • Highspeed — *a a = 25 ns max. commercial The CY7B210 is a high-performance 1-megabit BiFAMOS PROM organized in 64K words by 16 bits wide. It is available in
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CY7B210
40-pin,
600-mil
CY7B210
44-pin
CY7B210â
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C2021 m
Abstract: C2021 palc16r8 PALC16R 16R4 programming specification ic w6 sem 2015 ic equivalent PALC20 PALC16R6-30WMB
Text: K :Æ^ = PAL C20 Series r fÆ CYPRESS :.-. = Sr SEMICONDUCTOR Reprogrammable CMOS PALC 16L8,16R8,16R6,16R4 Features • CMOS EPROM technology for repro grammability • Higb performance at quarter power
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20-pin
PALC16R8-30KMB
PALC16R8-30LMB
PALC16R8-30QMB
PALC16R8--
30WMB
PALC16R8L-35LC
PALC16R8L-35PC
PALC16R8L-35VC
PALC16R8L-35WC
C2021 m
C2021
palc16r8
PALC16R
16R4 programming specification
ic w6
sem 2015 ic equivalent
PALC20
PALC16R6-30WMB
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C3317
Abstract: L1190 CY7331
Text: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all
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28-pin
28-Lead
28-Lead
300-Mil)
CY7C331
0Dlb56b
C3317
L1190
CY7331
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Untitled
Abstract: No abstract text available
Text: CY7C332 CYPRESS Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product term s (PTs) per output — Product term (PT) output polarity
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CY7C332
28-Square
CY7C332â
30TMB
28-Lead
30WMB
28-Lead
300-Mil)
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C2723
Abstract: C272-3
Text: CY7C272 PRELIMINARY = ¡ ^ 5 sr s c y p r e s s 1 SEMICONDUCTOR Features • 0.8-micron CMOS for optimum speed/ power • High speed — 25 ns max set-up — 25 ns clock to output • 16-bit-wide words • Registered outputs • Programmable synchronous or
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CY7C272
16-bit-wide
40-pin,
600-mil-wide
44-pin
CY7C272
16K-word
16-bit
It272â
C2723
C272-3
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Untitled
Abstract: No abstract text available
Text: CY7C291A CY7C292A/CY7C293A 'W CYPRESS = SEMICONDUCTOR Reprogrammable 2K x 8 PROM Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 2 0 ns commercial — 25 ns (military) • Low power — 660 mW (commercial and military)
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CY7C291A
CY7C292A/CY7C293A
300-mil
600-mil
CY7C291A,
CY7C292A,
CY7C293A
CY7C292Aâ
35DMB
CY7C293Aâ
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CY7C291A
Abstract: CY7C292A CY7C293A 57C29
Text: F# CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns commercial — 25 ns (military) CY7C291A CY7C292A/CY7C293A 2K X 8 Reprogrammable PROM • Direct replacement for bipolar PROMs • Capable o f withstanding >2001V stat
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CY7C291A
CY7C292A/CY7C293A
300-mil
600-mil
CY7C291A,
CY7C292A,
CY7C293A
300-mil
7C291A,
7C293A)
CY7C292A
57C29
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Untitled
Abstract: No abstract text available
Text: CY7B201 PRELIMINARY SEMICONDUCTOR Reprogrammable 128K x 8 Power-Down PROM Features Functional Description • BiFAMOS for optimum speed/ power • Highspeed — U a = 25 ns max. commercial — 1aa = 30 ns max. (m ilitary) • Low-power stand-by mode — 1210 mW max.
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CY7B201
32-pin,
600-mil
32-pin
CY7B201
30DMB
30LMB
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CY7C332-25HMB
Abstract: L9646 c3328 L9806 l9634 L9680 L480 L9622 L9626 L9823
Text: CY7C332 '0 C Y P R E S S F e a tu re s • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per output — Product terra (PT) output polarity
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CY7C332
CY7C332â
30LMB
28-Square
30TMB
28-Lead
30WMB
28-Lead
CY7C332-25HMB
L9646
c3328
L9806
l9634
L9680
L480
L9622
L9626
L9823
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20G10B-20
Abstract: 12L10 16L6 18L4 20L10 20L8
Text: r PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpn = 15 ns, tc o = ID us, tg = 12 ns — Military: tPD = 20 ns, tc o = 15 ns, ts — 15 ns • Low power — Ice max.: 70 mA, commercial — Ic e max.: 100 mA, military • Commercial and m ilitary tem perature
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PLDC20G10B/PLDC20G10
24-Pin
20L10,
12L10,
24-Lead
300-Mil)
PLDC20G10â
CG7C323
20G10B-20
12L10
16L6
18L4
20L10
20L8
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al p13
Abstract: CERAMIC LEADLESS CHIP CARRIER cerdip z PACKAGE cy7c291 CY7C293AL-35PC PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC CY7C291A CY7C292A CY7C293A
Text: CY7C291A CY7C292A/CY7C293A F# CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns commercial — 25 ns (military) 2K X 8 Reprogrammable PROM • Direct replacement for bipolar PROMs • Capable o f withstanding >2001V stat
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CY7C291A
CY7C292A/CY7C293A
300-mil
600-mil
CY7C291A,
CY7C292A,
CY7C293A
35QMB
CY7C293A-30WMB
CY7C293Aâ
al p13
CERAMIC LEADLESS CHIP CARRIER
cerdip z PACKAGE
cy7c291
CY7C293AL-35PC
PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC
CY7C292A
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RQW 130
Abstract: tlOH-tm33X ELLS 110 CY7C331
Text: i*bE ]> CYPRESS SEMICONDUCTOR B 256*^1.2 DDQ7Q5Q 7 Q C Y P c t 7C33i CYPRESS SEMICONDUCTOR Asynchronous Registered EPLD Features • Tnelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — O ne feedback flip-flop with input
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CT7C331
CY7C331-40QMB
CY7C331-40TMB
CY7C331-40WMB
DDQ7032
CY7C331
38-00066-C
RQW 130
tlOH-tm33X
ELLS 110
CY7C331
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7C293A
Abstract: 7C291A
Text: CY7C291A CY7C292A/CY7C293A î f CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns commercial 2K X 8 Reprogrammable PROM The CY7C291A, CY7C292A, and CY7C293A are plug-in replacem ents for bipolar devices and offer the advantages of
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CY7C291A
CY7C292A/CY7C293A
300-mil
600-mil
CY7C291A,
CY7C292A,
CY7C293A
7C293A--50WMB
7C293A--50TMB
7C293A--50QMB
7C293A
7C291A
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Untitled
Abstract: No abstract text available
Text: s rs 'w CY7C332 ~ •• = Registered Combinatorial EPLD CYPRESS — SEMICONDUCTOR Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per
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CY7C332
CY7C332â
30QMB
30TMB
30WMB
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