280II Search Results

54LS

Abstract: 74LS
Contextual Info: SWITCHING CHARACTERISTICS vCc - 5V, r A = 25°c T E S T CONDITIONS PARAMETER FROM INPUT TO OUTPUT Any MIN 54/74LS 54/74S C L =15pF R L = 2K îî C|_=15pF R|_=280ii TYP MAX MIN TYP MAX LEV ELS O F DELAY UNIT 2 ns Propagation delay time tp|_H Low-to-htgh Binary

74ls characteristics

Abstract: 74LS 74LS54 54LS 74ls 11
Contextual Info: S P E E D / P A C K A G E AVAILABILITY 54H F,W 54 L S F,W 54S F,W PIN CO NFIGURATION 74H A ,F 7 4 LS A ,F 7 4S A, F 74H.54/74LS.54/74S A,F,W PACKAGE vcc 2D P ositive logic: Y = A B C D N C -N o internal con n ectio n SW ITCHING C H A R A C T E R IS T IC S v CC =

Contextual Info: Signelìcs 7451, LS51, S51 Gates '51, S51 Dual 2-Wide 2-Input AND-OR-lnvert Gate LS51 Dual 2-Wlde 3-Input, 2-Wide 2-Input AND-OR-lnvert Gate Product Specification Logic Products FUNCTION TABLE '51, ’S51, h 'LS51 TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT

DM54S30

Abstract: DM54S30J DM54S30W DM74S30N J14A N14A W14B
Contextual Info: June 1989 DM54S30/DM74S30 8-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Connection Diagram Dual-In-Line Package Vcc I 14 NC H I 13 G NC 11 12 IMC 1 10 Y 19 8 — I 1 A 3 2 4 5 6 B C E F I7

Contextual Info: June 1989 Semiconductor D M 54S 64/D M 74S 64 4-W ide A N D -O R -IN V E R T G ates General Description This device contains a combination of gates which performs the logic AND-OR-INVERT function. Connection Diagram Dual-In-Line Package v ,:l n C B K . I V

IC AL 6001 audio ic

Abstract: pmi op37 IC AL 6001 20 pin IC AL 6001 audio ic 20 pin audio IC AL 6001 op37gp
Contextual Info: OP-37 PMi LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER AVCl ^ 5) M o n o l i t h i c s I nc . The OP-37 provides the low offset and d rift of the OP-07 plus higher speed and lower noise. O ffsets down to25/iV and d rift of 0.6mV/°C maximum make the OP-37 ideal fo r precision

Contextual Info: 75S207-F.N DESCRIPTION FEATURES The 75S207 is a high speed dual sense amplifier that is functionally equivalent and pin compatible to the SN75207. The im­ proved input sensitivity of ±10mV makes it suitable as a MOS memory sense amplifier which can result in faster memory cycles.

P3062-01

Abstract: hamamatsu photoreflector 3mm photo transistor P3062
Contextual Info: HAMAMATSU CORP ITE D • HESÌLDÌ HAMAMATSU OOOSbT? 7 ■ PHOTOREFLECTOR P3062-01 TECHNICAL DATA -^ /-7 3 Photo IC output digital output , Long focal distance (3mm), Thin package (4.0 x 4.2 x 1.7mm) The P3062-01 is a photoreflector combining a high-power in­

GP1A06

Abstract: circuit diagram for photointerrupter GP-1A06
Contextual Info: SHARP ELEK/ MELEC D I V I S E D | Photointerrupter GP1A06 aiöa?cia 0G03Gb7 q | _ G P1A0& T-41-73 Digital Output Type OPIC PhotointerruDter 2 -D h a s e Unit : mm O u tlin e D im ensions F eatu res Built-in Schmidt trigger circuit 2-phase digital output with phase differ­

74LSc

Abstract: 25C54
Contextual Info: SPEED /PACK AG E AVAILABILITY 54 F,W 74 PIN CONFIGURATION A,F A,F,W PACK AG E SWITCHING CHARACTERISTICS v C C 5V, t a = 25“ C □ * 54/74 □ = CL=15pF Rl =h o q T E ST CONDITIONS PARAMETER TYP MIN □ = MAX □ = UNIT □ Propagation delay time tp m Low-to-high

DS3647AN

Contextual Info: DS3647A ^National J y fl Semiconductor DS3647A Quad TRI-STATE MOS Memory I/O Register General Description The DS3647A is a 4-bit I/O buffer register intended for use in MOS memory systems. This circuit employs a fall-through latch for data storage. This method of latching captures the

DM54S32J

Abstract: DM54S32W DM74S32N J14A N14A W14B
Contextual Info: June 1989 Semiconductor DM54S32/DM74S32 Quad 2-Input OR Gates General Description This device contains four independent gates each of which performs the logic OR function. Connection Diagram Dual-In-Line Package Vcc | 14 B4 A4 13 Y4 12 B3 11 A3 10 9 Y3 8 3>i

Contextual Info: SGS-THOMSON ST14C02C SERIAL ACCESS CMOS 2K 256 x 8 EEPROM ADVANCE DATA MINIMUM 1 MILLION ERASE/WRITE CYCLES with OVER 10 YEARS DATA RETENTION SINGLE 3V to 5.5V SUPPLY VOLTAGE TWO WIRE SERIAL INTERFACE, FULLY l2C BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 4

Contextual Info: January 1992 DM74S132 Quad 2-Input Schmitt Trigger NAND Gate General Description This device contains four independent gates that perform the logic NAND function. Each gate has two inputs that are Schmitt Triggers. Connection Diagram T L /F /9 8 0 3 -1 Order Number DM74S132N

Contextual Info: S E M IC O N D U C T O R tm DM74S153 Dual 1 of 4 Line Data Selectors/Multiplexers • Perform s parallel-to-serial conversion General Description Each of these d ata selectors/m ultiplexers contains inverters and drivers to supply fully com plem entary, on-chip, binary

10nf electrolytic capacitor

Abstract: MAX873AESA
Contextual Info: 19-0038; Rev 1; 10/92 / i / i / j x i y i / i Low -Pow er, Low -D ri ft, + 2.5V /+5V /+10V Precision Voltage R eferences _ Features The MAX873/MAX875/MAX876 precision 2,5V, 5V, and 10V references offer excellent accuracy and very low

G3po

Abstract: CNY 14
Contextual Info: LOGIC DIAGRAM PIN CONFIGURATION B,F,W PACKAGE 3 3 I 3 4 VCC P ,[ T CO [7 NPUTS poE = [7 3^. ¡3=.-» 3a 3 P3 H OUTPUT P PUTS 7 ]c „ J GND [j[ INPUT/OUTPUT SCHEMATICS PIN DESIGNATIONS DESIGNATION PIN NOS. FUNCTION GO, G 1 .G 2 , G3 3, 1, 14, 5 Active-Low