25FITBB2 Search Results

7C188

Abstract: CY7C188
Contextual Info: CY7C188 • / CYPRESS 32K x 9 Static RAM Features Functional Description • High speed — 20 ns The CY7C188 is a high-perform ance CMOS static R A M organized as 32,768 words by 9 bits. Easy mem ory expansion is provided by an active-LOW chip enable C E j , an active-H IG H chip enable (C E2),

Contextual Info: Ei SST CY7C199 W f CYPRESS 32K x 8 Static RAM Features Functional Description • High speed — 12 ns • Fast tuoE • CMOS for optimum speed/power • Low active power — 880 mW • Low standby power — 165 mW • Easy memory expansion with CE and OE features

CY7C330-50TMB

Abstract: CY7C330 7C330
Contextual Info: CY7C330 '# C Y P R E S S Features • TVelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

Contextual Info: PRELIM INARY CY82C692 Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence

Contextual Info: /UHOU. i I/ o u / a u CY7C460 CY7C462 CY7C464 Revision: August 17,1994 F# CYPRESS Cascadable 8K x 9 FIFO Cascadable 16K x9F IF O Cascadable 32K x9F IF O Features Functional Description • 8K x 9 ,16K x 9 ,32K x 9 FIFO buffer memory • Asynchronous read/write

Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features • Provides control for the cache, system memory, and the PCI bus • PCI Bus Rev. 2.1 compliant • Supports 3V Pentium™, AMD K5, K6, and Cyrix 6x86 M1 CPUs • Support for WB or WT L1 cache

Contextual Info: CYPRESS SEMICONDUCTOR b5E T> 2 5 0 ^ 2 QQ1Q7T2 CYP CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR TÔ2 P rogram m ab le Skew C lock B u ffer P S C B Functional Description • Output pair skew <100 ps typical (250 max.) • All outputs skew <250 ps typical

333Q

Abstract: CY7C269 C2692
Contextual Info: CY7C269 CYPRESS Features • • C M O S for optim um speed/pow er • H igh speed com m ercial and m ilitary — 15-ns ad dress set-up • — 12-ns clock to output • O n-chip d iagn ostic sh ift register — For serial ob servability and con ­ trollab ility o f the ou tpu t register

bt ramdac

Abstract: 2062T YP167
Contextual Info: IC d esig n s Graphics Frequency Synthesizers ICD2062B Dual Programmable ECL/TTL Clock Generator Single-Chip Dual Programmable Oscillator Handles All Frequency Requirements of High-Performance Graphic Systems 2nd Generation Dual Oscilla­ tor Graphics Clock Generator

145-Pin

Contextual Info: fax id: 5600 VAC068A VMEbus Address Controller Features — Supports unaligned transfers • Optional companion part to VIC068A • Implements master/slave VMEbus interface in conjunc­ tion with the VIC068A • Complete VMEbus and I/O DMA capability for a 32-bit

STATIC RAM 6264

Abstract: ram 6264 Hyundai Semiconductor 6264 Hyundai 6264 DD172 CY6264
Contextual Info: CYPRESS PRELIMINARY CY6264 8K x 8 Static RAM Features active HIGH chip enable CE2 , and active LOW output enable (OE) and three-state • 55,70 ns access times drivers. Both devices have an automatic • CMOS for optimum speed/power power-down feature (CEi), reducing the

Contextual Info: CY7C330 '# C Y P R E S S CMOS Programmable Synchronous State Machine Three separate clocks— two inputs, one output Common pin 14-co n tro lled or product term —controlled output en­ able for each I/O pin 256 product terms—32 per pair of macrocells, variable distribution

programmer manual EPLD cypress

Contextual Info: l l lt fM d l l l t? . I U t? 5 U d y , M U y U 5 > l I I , ItKfcS Revision: Tuesday, June 28,1994 pASIC380 Family F/ CYPRESS Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz