256MBIT Search Results

GDDR

Abstract: K4D553238E-JC33 k4d553238e-jc40
Contextual Info: 256M GDDR SDRAM K4D553238E-JC 256Mbit GDDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 144-Ball FBGA Revision 1.3 August 2003 Samsung Electronics reserves the right to change products or specification without notice.

K4S561632C-TC/L75

Abstract: K4S561632C K4S561632C-TC K4S561632C-TC/L7C
Contextual Info: K4S561632C CMOS SDRAM 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.4 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.4 Sept. 2001 K4S561632C CMOS SDRAM Revision History

TRUEFFS

Abstract: toshiba toggle mode nand toshiba bios Diskonchip 1000H 800H
Contextual Info: ADVANCE INFORMATION Am71LVM032 32 MB Disk-on-Chip Single Chip Flash Memory and Disk Controller DISTINCTIVE CHARACTERISTICS • General — Flash Disk – full hard disk drive emulation — 32MByte 256Mbit capacity — Single die chip, based on 0.16 µm NAND flash

diskonchip

Abstract: MD3831-D16-V3Q18 diskonchip g4 MD3831-D16-V3Q18-X AP-DOC-057 smartphone MOTHERBOARD CIRCUIT diagram AD10 PR31700 password lock protection using mobile phone f Diskonchip Millennium Plus
Contextual Info: Data Sheet Mobile DiskOnChip Plus 16/32MByte 1.8V I/O Flash Disk, Protection and Security-Enabling Features Highlights Mobile DiskOnChip Plus 16/32MByte 128/256Mbit is one of the industry’s most efficient storage solutions, with the fastest write rates, the

dax6

Abstract: Mobile SDRAM
Contextual Info: V55C1256164MG 256Mbit MOBILE SDRAM 1.8 VOLT, TSOP II / FBGA PACKAGE 16M X 16 75 9 10 System Frequency fCK 133 MHz 111 MHz 100MHz Clock Cycle Time (tCK3) 7.5ns 9.0 ns 10 ns Clock Access Time (tAC3) CAS Latency = 3 6.0 ns 7.0 ns 8.0ns • Available in 54-ball FBGA (with 9x6 ball array

Contextual Info: V54C3256 16/80/40 4VD*I 256Mbit SDRAM, INDUSTRIAL TEMPERATURE 3.3 VOLT, TSOP II / FBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3

Contextual Info: V54C3256 16/80/40 4VD 256Mbit SDRAM 3.3 VOLT, TSOP II / FBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns

9.1 b3

Contextual Info: V59C1256 404/804/164 QA*I HIGH PERFORMANCE 256Mbit DDR2 SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 16Mbit X 4 (404) 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) PRELIMINARY 37 3 25 DDR2-533 DDR2-667 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4)

Contextual Info: V54C3256 16/80/40 4VH 256Mbit SDRAM 3.3 VOLT, TSOP II / FBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 6 7PC 7 System Frequency (fCK) 166 MHz 143 MHz 143 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns 5.4 ns Clock Access Time (tAC2) CAS Latency = 2

9.1 b3

Contextual Info: PRELIMINARY V59C1256 404/804/164 QA HIGH PERFORMANCE 256Mbit DDR2 SDRAM 4 BANKS X 16Mbit X 4 (404) 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 37 3 25A 25 DDR2-533 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4)

K4S561632C

Contextual Info: K4S561632C CMOS SDRAM 256Mbit SDRAM Extended Temp Support 4M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.1 Sept.2001 K4S561632C CMOS SDRAM

marking code EY SMD

Abstract: PC100-222-620 P-TSOPII-54
Contextual Info: HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 256 MBit Synchronous Low-Power DRAM Data Sheet Revision Dec. 2002 • Automatic and Controlled Precharge Command Features -7.5 -8 Units fCK,MAX 133 125 MHz • Programmable Burst Length: 1, 2, 4, 8 and full page tCK3,MIN

39S256160T

Abstract: TSOP54-2 APA10 39S256160T-8 39S256400T-8
Contextual Info: H YB39S25640x/80x/16xT 256MBit Synchronous DRAM SIEMENS 256 MBit Synchronous DRAM Target Information Rev. 0.6 • High Performance: Multiple Burst Operation -8 -10 Units fCK 125 100 MHz tCK3 8 10 ns tAC3 6 7 ns Automatic Command and Read with Single Controlled

Contextual Info: DATA SHEET 512MB Registered DDR SDRAM DIMM HB54A5129F1-B75B/10B 64M words x 72 bits, 1 Rank Features The HB54A5129F1 is a 64M × 72 × 1 rank Double Data Rate (DDR) SDRAM Module, mounted 18 pieces of 256Mbits DDR SDRAM sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver

Contextual Info: PRELIMINARY DATA SHEET 1GB Registered DDR SDRAM DIMM HB54R1G9F2U-A75B/B75B/10B 128M words x 72 bits, 2 Banks Description Features The HB54R1G9F2U is a 128M × 72 × 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of 256Mbits DDR SDRAM (HM5425401BTB) sealed in

Contextual Info: K4S560832C CMOS SDRAM 256Mbit SDRAM Super low power 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 0.5 Nov. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.5 Nov. 2001 K4S560832C CMOS SDRAM Revision History

PC133-333-520

Abstract: PC100-222 PC133-222 PC133-333 L-DIM-168-33 PC133 registered reference design
Contextual Info: HYS 64/72V32300GU SDRAM-Modules 3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules • Single + 3.3 V ± 0.3 V power supply • 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications using 256Mbit technology.

Contextual Info: 256M gDDR2 SDRAM K4N56163QG 256Mbit gDDR2 SDRAM Revision 1.1 April 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: 256M GDDR3 SDRAM K4J55323QG 256Mbit GDDR3 SDRAM Revision 1.2 March 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: K4S560832C CMOS SDRAM 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Mar. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Mar. 2001 K4S560832C CMOS SDRAM Revision History Revision 0.0 Mar. 06, 2001

GDDR

Abstract: K4D551638H-LC50
Contextual Info: K4D551638H 256M GDDR SDRAM 256Mbit GDDR SDRAM Revision 1.3 April 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: KM44S64230A CMOS SDRAM 256Mbit SDRAM 16M X 4bit X 4 Banks Synchronous DRAM LVTTL Revision 0.2 January 1999 Samsung Electronics reserves the right to change products or specification without notice. REV. 0.2 Jan. '99 KM44S64230A CMOS SDRAM R evision H isto ry

V54C3256

Contextual Info: MOSEL VITELIC V54C3256 16/80/40 4V(T/C) 256Mbit SDRAM 3.3 VOLT, TSOP II / TRUECSP PACKAGE 16M X 16, 32M X 8, 64M X 4 PRELIMINARY 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3

Contextual Info: MOSEL VITELIC V54C3256 16/80/40 4V(T/S/B) 256Mbit SDRAM 3.3 VOLT, TSOP II / SOC / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 PRELIMINARY 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3