250OHMS Search Results

LCD Drivers

Abstract: AD8509 AD8511 2204
Contextual Info: AMPLIFIERS: LCD DRIVERS LCD Drivers MODEL NUMBER # CH AD8509 AD8511 11/10/98 9 11 Vdd Idd Eos Ib Gain Volts 5 5 mA 8.5 10 mV 20 20 nA 50 50 V/Volt 0.985 0.985 8:58 AM -3dB BW Mhz Slew Rate V/usec 5 5 Settling Rl=250ohms usec 6.2 6.2 ED GROKULSKY Settling Cl=15pF

bzx 850

Abstract: bzx 850 30
Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

Contextual Info: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

CY7C1620KV18-250BZXC

Contextual Info: CY7C1618KV18, CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18, 8 M × 36 CY7C1618KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth

Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18

Contextual Info: CY7C1518KV18, CY7C1520KV18 72-Mbit DDR II SRAM Two-Word Burst Architecture 72-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18, 2 M × 36 CY7C1518KV18 – 4 M × 18 ■ 333 MHz clock for high bandwidth CY7C1520KV18 – 2 M × 36

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-06981 Spec Title: CY7C1523AV18/CY7C1524AV18, 72-MBIT DDR II SIO SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar NJY Replaced by: None CY7C1523AV18 CY7C1524AV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture

7N19

Abstract: CY7C1316AV18 CY7C1318AV18 CY7C1320AV18
Contextual Info: CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at

CY7C1316BV18

Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
Contextual Info: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1413JV18 CY7C1415JV18 36-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1413JV18 – 2M x 18 ■ 300-MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency

SSM3302

Contextual Info: Evaluation Board User Guide UG-360 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluation Board for SSM3302 2 x 10 W Filterless Class-D Stereo Audio Amplifier PACKAGE CONTENTS

Contextual Info: CY7C1546KV18, CY7C1557KV18 CY7C1548KV18, CY7C1550KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.0 cycles: ■ 450 MHz Clock for High Bandwidth

Contextual Info: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 兆2-Mb典t唯Q当R 唯存存唯止RAM唯2唯 • ■ J正AG唯114版.1唯 ■ 唯样PLL核 ❐ ■ 350唯M字争唯 唯2唯 ■ ■ 唯样当当R核唯 唯 唯兆00唯M字争唯 K唯 ■ ❐ 唯K 唯350 M字争

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-06348 Spec Title: CY7C1248V18, CY7C1250V18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Sunset Owner: Jayasree Nayar Replaced by: None CY7C1248V18 CY7C1250V18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-06582 Spec Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT QDR TM -II+ SRAM 4-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Jayasree Nayar (njy) Replaced by: NONE CY7C1161V18, CY7C1176V18

CY7C1411BV18

Abstract: CY7C1413BV18 CY7C1415BV18 CY7C1426BV18
Contextual Info: CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■

CY7C1510AV18

Abstract: CY7C1512AV18 CY7C1514AV18 CY7C1525AV18 CY7C1512AV18-167BZXC
Contextual Info: CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1510AV18 – 8M x 8 ■ 250 MHz clock for high bandwidth

CY7C1422AV18

Abstract: CY7C1423AV18 CY7C1424AV18 CY7C1429AV18
Contextual Info: CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

CY7C1311CV18

Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■

05564

Abstract: CY7C1522V18 CY7C1523V18 CY7C1524V18 CY7C1529V18
Contextual Info: CY7C1522V18, CY7C1529V18 CY7C1523V18, CY7C1524V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

CY7C1546V18

Abstract: CY7C1548V18 CY7C1550V18 CY7C1557V18
Contextual Info: CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) ■ 300 MHz to 375 MHz clock for high bandwidth ■

CY7C1520V18-200BZXC

Abstract: CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18
Contextual Info: CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

CY7C1512V18-250BZXC

Abstract: CY7C1510V18 CY7C1512V18 CY7C1514V18 CY7C1525V18
Contextual Info: CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth