24JAN2005 Search Results

408-2187

Abstract: shv rg 174 PLUG 5051426-2
Contextual Info: 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT 2 3 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. - LOC ALL RIGHTS RESERVED. REVISIONS DIST 6 AJ LTR DESCRIPTION 1. R ELEASED PER DATE OS14 - 0 4 9 6 - 0 4 SEE INSTRUCTION DWN 24JAN2005 APVD JGH JL SHEET 4 0 8 - 2 1 8 7

6206a

Abstract: K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e
Contextual Info: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

RF connector plug spec

Abstract: SHV CONNECTOR 220022-1 5051426-2 HA20
Contextual Info: 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT 2 3 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. - LOC ALL RIGHTS RESERVED. REVISIONS DIST 6 AJ LTR DESCRIPTION A1 1. D REVISED PER E C O - 0 6 - 0 0 4 2 5 0 SEE INSTRUCTION DATE DWN APVD 28FEB2006 KS

STK 411-550 E

Abstract: stk power amplifiers 411-550 UM0404 st10 Bootstrap datasheet STK 411-550 E 221-550 st10f276 jtag DIS12 ST10F276 CAN bit timing ST10
Contextual Info: UM0404 User manual ST10F276 Introduction This manual describes the functionality of the ST10F276 device. An architectural overview describes the CPU performance, the on-chip system resources, the on-chip clock generator, the on-chip peripheral blocks and the protected bits.

Contextual Info: THIS DRAWING IS UNPUBLISHED. ART WV COPYRIGHT - 6 7 8 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. 5 2 3 - LOC ALL RIGHTS RESERVED. DIST AJ R E V IS IO N S 16 P LTR DESCRIPTION R ELEASED PER DATE DWN 27JAN2005 0S 1 4 - 0 4 9 6 - 0 4 APVD JGH JL

spec RG-179

Abstract: 220190-1
Contextual Info: 6 7 THIS DRAWING IS UNPUBLISHED. COPYRIGHT - 4 3 2 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. LOC ALL RIGHTS RESERVED. DIST AJ R E VIS IO N S 16 LTR DESCRIPTION RELEASED PER 0S1 4 - 0 4 9 6 - 0 4 D 1 . USE 2. M A X IM U N IN S T R U C T IO N

220190-1

Abstract: spec cable RG-174 amp 220190-1
Contextual Info: 6 7 THIS DRAWING IS UNPUBLISHED. COPYRIGHT - 5 3 2 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. LOC ALL RIGHTS RESERVED. AJ DIST R E VIS IO N S 16 LTR DESCRIPTION DATE RELEASED PER 0S1 4 - 0 4 9 6 - 0 4 DWN APVD JGH JL 2 7 JA N 2 0 0 5 D D USE

st10f296

Abstract: st10f296 boot marking code W1p st10 Bootstrap 15B3 ST339
Contextual Info: ST10F296E 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM Features • ■ High performance 16-bit CPU with DSP functions – 31.25 ns instruction cycle time at 64 MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit multiplication, 40-bit accumulator

"Phantom power"

Contextual Info: INA163 SBOS177C – NOVEMBER 2000 – REVISED JANUARY 2005 Low-Noise, Low-Distortion INSTRUMENTATION AMPLIFIER FEATURES DESCRIPTION ● ● ● ● ● ● ● The INA163 is a very low-noise, low-distortion, monolithic instrumentation amplifier. Its current-feedback

OA 161 diode

Abstract: 74VCXHQ163245R-E 74VCXHQ163245TBR 74VCXHQ163245TTR TSSOP48 74VCXHQ163245 74VCXHQ163245LBR
Contextual Info: 74VCXHQ163245 16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH BUS HOLD AND EMI NOISE CONTROL • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD =6.0ns MAX. at TA=85°C VCCA = 3.0V VCCB = 2.3V; Bn to An LOW POWER DISSIPATION: ICCA = ICCB = 20µA(MAX.) at TA=85°C

Contextual Info: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

Contextual Info: 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT 3 RELEASED BY TYCO ELECTRONICS CORPORATION. FOR PUBLICATION - 2 - LOC ALL RIGHTS RESERVED. DIST AJ R EVIS IO N S 6 P LTR DESCRIPTION DATE RELEASED PER 0S1 4 - 0 4 9 6 - 0 4 DWN APVD JGH JL 25JAN2005 D D ZIN C QQ-Z-363.

RG-179

Contextual Info: 3 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT RELEASED BY TYCO ELECTRONICS CORPORATION. FOR PUBLICATION - 2 - LOC ALL RIGHTS RESERVED. AJ REVISIONS DIST 17 LTR DESCRIPTION DATE RELEASED PER 0S1 4 - 0 4 9 6 - 0 4 DWN 2 5 JA N 2 0 0 5 APVD JGH JL D D USE CRIMP TOOL:

Contextual Info: AMP 460 5 REV 3 1 MAR2000 LOC REVISIONS D IS T CM 00 LTR DESCRIPTION H 1. PARTS A. DIMENSIONS /5 \ COMPLY WITH AMP C IR C U IT IN A BRACKETS ARE IDENTIFICATION BUT LOCATION SOLDERABILITY AND IN KW SR 25JAN05 SPECIFICATION 1 0 9 - 1 1 - 3 . MAY ARE A D J A C E N T TO T H E

mdc 3052

Abstract: ST10F276E ST10F276-6QR3 W1P 51 w1p 66 K-Line L line TQFP144 DIMENSION st10 Bootstrap ST10F2xx transistor w2P
Contextual Info: ST10F276E 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

5221221-7

Contextual Info: THIS DRAWING IS UNPUBLISHED. COPYRIGHT - RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. LOC DIST AJ ALL RIGHTS RESERVED. R E VIS IO N S 16 LTR DESCRIPTION A1 [. 2 RECOMMENDED 12 . + 0.1 3 0.00 3 4 IN S T R U C TIO N REVISED PER ECO 0 9 - 0 0 6 1 7 3

transistor w2P

Abstract: diode T35 12H st10f276 jtag TQFP144 reel size ST10F276E l 7251 3.1 st10f276 TQFP144 DIMENSION transistor w1P W1P 51
Contextual Info: ST10F276E 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM Features • ■ ■ ■ ■ ■ Highly performant 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

74VCXHQ163245

Abstract: 74VCXHQ163245LBR 74VCXHQ163245R-E 74VCXHQ163245TBR 74VCXHQ163245TTR TSSOP48
Contextual Info: 74VCXHQ163245 16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH BUS HOLD AND EMI NOISE CONTROL • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD =6.0ns MAX. at TA=85°C VCCA = 3.0V VCCB = 2.3V; Bn to An LOW POWER DISSIPATION: ICCA = ICCB = 20µA(MAX.) at TA=85°C

arinc 404

Abstract: 205117-2
Contextual Info: 4 TH IS DRAWING IS U N P U B LIS H E D . RELEASED FOR PUBLICATION A L L RIGHTS COPYRIGHT 2 3 - LOC D IST DF AO RESERVED. BY TYCO ELECTRONICS CORPORATION. REVISIONS LTR D E SC RIPTIO N REV PER 1 .24 5 D EC OH1 4 - 0 1 5 4 - 0 4 2051 1 7 - 1 1 . AS 205117-2

d2nk7

Abstract: STD2NK70Z STD2NK70Z-1 STD2NK70ZT4
Contextual Info: STD2NK70Z - STD2NK70Z-1 N-CHANNEL 700 V - 6 Ω - 1.6 A DPAK/IPAK Zener-Protected SuperMESH MOSFET Figure 1: Package Table 1: General Features TYPE VDSS RDS on ID Pw STD2NK70Z STD2NK70Z-1 700 V 700 V 7Ω 7Ω 1.6 A 1.6 A 45 W 45 W • ■ ■ ■ ■

UM0381

Abstract: programmer st10f272 RH3 439 ST10F272 OSC32 ST10F276 CAN bit timing st10 Bootstrap ACC20 ST10 half adder
Contextual Info: UM0381 User manual ST10F272 Introduction This manual describes the functionality of the ST10F272 devices. An architectural overview describes the CPU performance, the on-chip system resources, the on-chip clock generator, the on-chip peripheral blocks and the protected bits.

Contextual Info: r 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT 3 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. — 2 - LOC ALL RIGHTS RESERVED. AJ DIST R E V IS IO N S 17 P LTR DESCRIPTION A R E V IS E D PER EC 0S1 4 - 0 1 5 0 - 0 5 DATE DWN APVD 30AUG05 BM JL

ASTM-B36

Abstract: ASTM-B-488 ASTM-D1710 ASTM-D-1710 ASTM-B16 ASTM-B-36
Contextual Info: 4 THIS DRAWING IS UNPUBLISHED. 3 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. COPYRIGHT 155 .0 1 O D 2 LOC ALL RIGHTS RESERVED. 325 AJ R E V IS IO N S DIST 53 LTR MAX DESCRIPTION RELEASED PER 0 S 1 4 - 0 4 9 6 - 0 4 . 1\ B R A S S CONTACT MAX

ASTM-B-139

Contextual Info: 3 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT RELEASED BY TYCO ELECTRONICS CORPORATION. FOR PUBLICATION - 2 - LOC ALL RIGHTS RESERVED. REVISIONS DIST 6 AJ LTR DESCRIPTION DATE RELEASED PER 0S1 4 - 0 4 9 6 - 0 4 DWN 2 5 JA N 2 0 0 5 APVD JGH JL D D ZIN C C