2048KBIT Search Results

Contextual Info: IßTEXAR X R -T 6 166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The XR-T6166 is a digital CM O S circuit which performs the interface function betweeh a 64kbit/s data stream and a 2048kbit/s PCM timeslot data channel. When

MH89793

Abstract: MT8979 MT9079
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

Contextual Info: MH89792 MITEL E1 Line Interface Unit LIU Preliminary Information Features • ISSUE 4 Complete prim ary rate 2048kbit/s E1 line driver and receiver with clock recovery MH89792-1 MH89792-2 Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transm it and

Contextual Info: J T E X A R XR-T6165 Codirectional Digital Data Processor PIN ASSIGNMENT GENERAL DESCRIPTION The XR-T6165 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in

clock alarm circuit diagram

Contextual Info: 22* E X 4 R XR-T6166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The XR-T6166 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in

MH89793

Abstract: MT8979 MT9079
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

MH89793

Abstract: MT8979 MT9079 zarlink PDIP
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

Contextual Info: MH89792 E1 Line Interface Unit LIU Data Sheet Features DS5712 Issue 4 March 2002 Ordering Information • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery • Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and

MH89792

Abstract: MH89792-1 MH89792-2 MT8979 MT9041 MT9079 PCM30 RJ48C
Contextual Info: MH89792 E1 Line Interface Unit LIU Data Sheet Features DS5712 Issue 4 March 2002 Ordering Information • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery • Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and

MH89793

Abstract: MT8979 MT9079 EW 90
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

Contextual Info: EX4R XR-T6165 Codirectional Digital Data Processor PIN ASSIGNMENT GENERAL DESCRIPTION The XR-T6165 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in conjunction with the XR-T6164, the XR-T6165 conforms

Contextual Info: E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features ISSUE 2 • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery • Meets ETSI requirements [ETSI ETS 300 011, NET 5] • Built-in selectable term ination impedance

Contextual Info: XR-T6166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM G EN ERA L DESCRIPTION The XR-T6166 is a digital CM OS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM tim eslot data channel. When used in

MH89793

Abstract: MT8979 MT9041 MT9079 PCM30 RJ48C RZA 18 RJ48
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information  Features ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

Zarlink Pin Compatible

Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

MH89792

Abstract: MH89792-1 MH89792-2 MT8979 MT9041 MT9079 PCM30 RJ48C VOH24
Contextual Info: MH89792 E1 Line Interface Unit LIU Data Sheet Features DS5712 Issue 4 March 2002 Ordering Information • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery • Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and

RXB 24

Abstract: MH89792 MH89792-1 MH89792-2 MT8979 MT9041 MT9079 PCM30 RJ48C
Contextual Info: MH89792  E1 Line Interface Unit LIU Preliminary Information ISSUE 4 Features • • • • • • • • • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and

RXB 24

Contextual Info: MH89792 E1 Line Interface Unit LIU Data Sheet Features DS5712 Issue 4 March 2002 Ordering Information • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery • Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and

MT90812AL1

Abstract: TGE-5 EB32
Contextual Info: MT90812 Integrated Digital Switch IDX Advance Information Mar 2011 Features • • • • • • • • • • • • • • • • • • MT90812AP MT90812AL MT90812APR MT90812AP1 MT90812AL1 MT90812APR1 192 channel x 192 channel non-blocking switching

ftz 951

Abstract: G793 G-743
Contextual Info: Frame and Line Interface Component FALC 54 PEB 2254 General Information The Frame and Line Interface Component PEB 2254 (FALC54) is a high sophisticated single chip solution for primary rate PCM carriers. It may be programmed to operate in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems.

PEB2255

Abstract: irs5 PXB4219E PXB4220 PXB4220E PXB4221 PXB4221E PXB4219 TINI microcontroller cards
Contextual Info: P re li mi na ry D ata S he et , DS 1, J ul y 20 01 IW E 8 In te r wo r k i n g E le m en t f or 8 E 1/ T1 L i ne s P XB 4 2 19 E /P X B 4 22 0 E/ P X B 42 21 E V er s i o n 3. 4 Da ta c o m N e v e r s t o p t h i n k i n g . Edition 2001-07 Published by Infineon Technologies AG,

Contextual Info: vm IMP8980D PCM Digital Switch General Description Functional Description This CMOS device is designed for switching PCM -encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up

TDD 1605

Abstract: lt 6029 PLCC-44 cr16 0.8um tg-500 L3000N L3000S PLCC44 SEL24 STLC3040
Contextual Info: STLC3040 S U BSC R IBER LINE INTERFACE CODEC FILTER, CO FISLIC PRELIM IN ARY DATA PLCC44 O RDERING NUM BER: STLC3040FN Figure 1 : Pin Connection Top view o > [ « [ <° \ Single chip CODEC and FILTER including all LOW-VOLTAGE SLIC functions. Advanced 12V BJT, 5V CMOS 0.8um technol­