1987R Search Results

Contextual Info: SN74BCT29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER S C B S 257- SEPTEMBER 1987 - REVISED NOVEMBER 1993 DW OR NT PACKAGE • BICMOS Process With TTL Inputs and Outputs T O P V IE W • State-of-the-Art BICMOS Design Significantly Reduces Standby Current

Contextual Info: SN54F20, SN74F20 DUAL 4-INPUT POSITIVE-NAND GATES D2932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs S N 5 4 F 2 0 . . . J PACKAGE S N 7 4 F 2 0 . . . 0 OR N PACKAGE

sn74f160

Abstract: SN54F160
Contextual Info: SN 54F160A, SN 54F162A, SN 74F160A, SN 74F162A SYNCHRONOUS 4-BIT DECADE COUNTERS D2932, MARCH 1987-REVISED JANUARY 1989 • Internal Look-Ahead for Fast Counting • Carry O utput fo r n-Bit Cascading • Fully Synchronous Operation for Counting • Package Options Include Plastic "Sm all

LP319

Abstract: IC 74LS00
Contextual Info: I IP 11Q IP7Q 11 LOW POW ER QUAD D IFFER EN TIA L C OM PARATORS 030 44 , OCTOBER 1987-REVISED MAY 1988 • Ultralow Power Supply Current Drain . . . Typically 6 0 /»A • Low Input Biasing Current . . . 3 nA D, J, OR N PACKAGE (TOP VIEW • Low Input Offset Current . . . ± 0 .5 nA

Contextual Info: SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056A - D2932, MARCH 19B7-REVISED OCTOBER 1993 • Internal Look-Ahead Circuitry for Fast Counting • Carry Output for N-Bit Cascading D OR N PACKAGE TOP VIEW • Fully Synchronous Operation for Counting • Package Options Include Plastic

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: SN54F30, SN74F30 8-INPUT POSITIVE-NANO GATES D2932, MARCH 1987-R E V ISE D JANUARY 1989 SN 54F30 . . . J PACKAG E SN 74F30 D OR N P A C K A G E Package Options Includa Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mII

051b

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B - MARCH 1987 - REVISED JULY 1996 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54F13 8 . . . J PACKAGE SN74F138. . . D OR N PACKAGE TOP VIEW u Incorporates Three Enable Inputs to

c4885

Contextual Info: TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP S C T S 0 2 1 C - A U G U S T 1 9 8 7 - R E V IS E D J U L Y 1996 Reliable Slllcon-Gate CMOS Technology DW OR N PACKAGE T O P V IE W Low Power Consumption - Operating M o d e . . . 80 mW

Contextual Info: SN54F11, SN74F11 TRIPLE 3-INPUT POSITIVE-ANO GATES D2932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mll DIPs SN64F11 . . . J PACKAGE SN74F11 . . . D OR N PACKAGE

SN74F138

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051 A - D2932, MARCH 1987 - REVISED OCTOBER 1993 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

dallas 2505

Abstract: LT1009M LM136-2.5
Contextual Info: LT1009 2.5-V INTEGRATED REFERENCE CIRCUIT D3191, MAY 1987-REVISED AUGUST 1991 Excellent Temperature Stability LT1009C, LT1009I. . . D PACKAGE TOP VIEW Initial Tolerance . . . 0.2% Max NC[ NC[ N C[ AN O D E[ Dynamic Impedance . . . 0.6 Q Max Wide Operating Current Range

51132L

Contextual Info: SN54F299, SN74F299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS D2932, MARCH 1987-REVISED JANUARY 1989 Four Modes of Operation: Hold Store , Shift Right, Shift Left, and Load Data SN 54F299 . . . J PACKAGE SN 74F299 . . . DW OR N PACKAGE (TOP VIEW!

D2957

Abstract: 1987-REVISEDAPRIL
Contextual Info: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted

54f620

Contextual Info: SN54F620 THRU SN54F623, SN74F620 THRU SN74F623 OCTAL BUS TRANSCEIVERS D2932, MARCH 1987-REVISED JANUARY 1969 Local Bus-Latch Capability SN54F' . . . J PACKAGE SN74' . . . DW OR N PACKAGE Choice of Inverting or Noninverting Logic TOP VIEW! Choice of 3-State or Open-Collector Outputs

Contextual Info: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process

b4f25

Abstract: SN54F251A 64f25
Contextual Info: SN54F251A, SN74F251A 1-0F-8 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS D2932, MARCH 1987-REVISED JANUARY 1989 SN 54F251A . . . J PACKAGE S N 74F251A . . . D OR N PACKAGE Three-State Versions of SN54F151A and SN74F151A TOP VIEW} Three-State Outputs Interface Directly with

Contextual Info: 54ACT11534,74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCASQ38A- D2957, JULY 1987 - REVISED APRIL 1883_ logic diagram positive logic logic symbolt 24 55 rs 13 >C 1 CLK n 1D r i 2 2D _ _ 1Q 1Q 1D •V 20 3 4

Contextual Info: SN54BCT2827B, SN74BCT2827B 10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE OUTPUTS D2977, APRIL 1987-REVISED JULY 1990 SN54BCT2827B . . . JT PACKAGE SN74BCT2B27B . . . DW OR NT PACKAGE BICM OS Design S ubstantially Reduces 'c c z TOP VIEW O utput Ports Have E quivalent 25-Q

74AC11646

Abstract: D2957
Contextual Info: 74AC11646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ P2957, JULY 1987 - REVISED APRIL 1993 * Independent Registers for A and B Buses * Multiplexed Real-Time and Stored Data * Flow-Through Architecture Optimizes PCB Layout

DS3896

Abstract: DS3897 SN75 SN75ALS056 SN75ALS057 d3615 a789 D2318
Contextual Info: SN55ALS056, SN55ALS057, SN75ALS056, SN75ALS057 TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS _SLLS028D- D3025, AUGUST 1987- REVISED MARCH 1993 SUITABLE FOR IEEE STANDARD 896 APPLICATIONSt SN55ALS056 and SN75ALS056 are Octal

tm5320

Abstract: "saturation value" E2242 s27c64
Contextual Info: TMS320 SECOND-GENERATION DIGITAL SIGNAL PROCESSORS MAY 1987-REVISED MAY 1989 68-PIN GB PACKAGE* 80-ns Instruction Cycle Time TOP VIEW 544 Words of On-Chip Data RAM 3 4 5 6 7 8 9 10 11 • 4K Words of On-Chip Program ROM (TMS320C25) • 128K Words of Data/Program Space

UTC 494 equivalent

Abstract: 74AC11520 D2957
Contextual Info: TEXAS INSTR LOGIC 31E D H 6^1753 □DflflflfiB h • TII3 54A C11520, 74A C11520 8-BIT IDENTITY C O M PA R A TO R S - t - i s - n - o o TI0099— D2957, JULY 1987—REVISED JANUARY 1990 • Compares Two 8-Bit Words 54AC11520 . . . J PACKAGE 74AC1152Q . . . DW OR N PACKAGE